Patents by Inventor Hiroshi Takatori

Hiroshi Takatori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10374782
    Abstract: A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventor: Hiroshi Takatori
  • Publication number: 20190024855
    Abstract: This luminous flux control member has: a plane of incidence having a first incidence plane and a second incidence plane; an emission plane; and a second concavity. The luminous flux control member satisfies the expression h1<h2+d√ócot(?1+?2), where h1 is the space between the apex of the second concavity and a second imaginary line orthogonal to the center axis and that passes through the aperture edge portion, h2 is the space between the second imaginary line and the incidence position of light on the second incidence plane, d is the distance between the incidence position and the apex in the direction orthogonal to the center axis, ?1 is the angle of refraction of light in the incidence position, and ?2 is the angle of the tangent line at the incidence position in relation to the second imaginary line.
    Type: Application
    Filed: August 29, 2016
    Publication date: January 24, 2019
    Inventors: Toshihiko MOCHIDA, Hiroshi TAKATORI
  • Patent number: 10135548
    Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 20, 2018
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Hiroshi Takatori, Zhan Duan, Purackal M. Mammen
  • Patent number: 10056887
    Abstract: An apparatus and method are provided for controlling a delay circuit. Included is a delay circuit configured to receive a probe signal. Further provided is a controller in electrical communication with the delay circuit. The controller is configured to perform various operations, in response to the receipt of the probe signal by the delay circuit. A positive peak and a negative peak of an output of the delay circuit are measured. Further, a ratio involving the positive peak and the negative peak of the output of the delay circuit is calculated. A delay of the delay circuit is controlled, based on the ratio.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 21, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventor: Hiroshi Takatori
  • Patent number: 9960899
    Abstract: A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 1, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventor: Hiroshi Takatori
  • Patent number: 9917663
    Abstract: An apparatus, system, and method are provided for configuring a serializer/deserializer (SerDes) based on evaluation of a probe signal. Included is circuitry configured to detect at least one of a probe signal or a reflection resulting from the probe signal. Such probe signal and/or reflection is evaluated such that at least one configurable aspect of the apparatus may be set, based on the evaluation.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: March 13, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hiroshi Takatori, Kevin Zheng, Zhan Duan
  • Publication number: 20180069646
    Abstract: An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 8, 2018
    Inventor: Hiroshi Takatori
  • Publication number: 20180069541
    Abstract: An apparatus and method are provided for controlling a delay circuit. Included is a delay circuit configured to receive a probe signal. Further provided is a controller in electrical communication with the delay circuit. The controller is configured to perform various operations, in response to the receipt of the probe signal by the delay circuit. A positive peak and a negative peak of an output of the delay circuit are measured. Further, a ratio involving the positive peak and the negative peak of the output of the delay circuit is calculated. A delay of the delay circuit is controlled, based on the ratio.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 8, 2018
    Inventor: Hiroshi Takatori
  • Patent number: 9900121
    Abstract: An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 20, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventor: Hiroshi Takatori
  • Publication number: 20180048401
    Abstract: An apparatus, system, and method are provided for configuring a serializer/deserializer (SerDes) based on evaluation of a probe signal. Included is circuitry configured to detect at least one of a probe signal or a reflection resulting from the probe signal. Such probe signal and/or reflection is evaluated such that at least one configurable aspect of the apparatus may be set, based on the evaluation.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Hiroshi Takatori, Kevin Zheng, Zhan Duan
  • Publication number: 20180048396
    Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Hiroshi Takatori, Zhan Duan, Purackal M. Mammen
  • Patent number: 9753211
    Abstract: A light emitting device includes a substrate in which a specular reflection area that specularly reflects reaching light is disposed on one surface, a light emitting element disposed on the substrate to emit light at least from a side surface, and a light flux controlling member disposed over the light emitting element to control a distribution of light to be emitted from the light emitting element. The light flux controlling member includes a rear surface disposed closer to the substrate, an incidence surface being an inner surface of a recess opening toward the rear surface and receiving light emitted from the light emitting element, and an emission surface emitting at least a part of the light incident through the incidence surface toward an outside. An outer edge portion of the specular reflection area is positioned outside an opening edge portion of the recess.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: September 5, 2017
    Assignee: ENPLAS CORPORATION
    Inventors: Hiroshi Takatori, Yu Kamijo
  • Publication number: 20170207901
    Abstract: A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventor: Hiroshi Takatori
  • Patent number: 9683719
    Abstract: This luminous flux control member has: an incidence surface through which light emitted from a light-emitting element enters; an emission surface through which the light entering from the incidence surface is emitted to the outside; and multiple ridges that are formed on the back side so as to surround the central axis (CA) and that have a substantially triangular cross-sectional shape. Each of the multiple ridges has a first reflecting surface, a second reflecting surface, and a ridge line which is the line of intersection of the first reflecting surface and the second reflecting surface. An imaginary line containing the ridge lines intersects the central axis (CA) at a position closer to the front side than the ridge lines.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: June 20, 2017
    Assignee: ENPLAS CORPORATION
    Inventor: Hiroshi Takatori
  • Patent number: 9641311
    Abstract: An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising a first transmitter configured to send first data at a data rate to a second receiver in a second IC, a first receiver configured to receive second data at the data rate from a second transmitter in the second IC, wherein each of a first link and a second link is to the first transmitter, the first receiver, the second transmitter, and the second receiver, and wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 2, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventor: Hiroshi Takatori
  • Patent number: 9641286
    Abstract: A transmitter including a noise signal generator and a summing element is provided. The noise signal generator is configured to receive multiple noise settings and output multiple noise signals corresponding to the multiple noise settings. The summing element is configured to receive a transmit data signal and the multiple noise signals, sum one or more of the multiple noise signals with the transmit data signal, and output to a transmit driver configured to generate one of a single-ended and a differential signal based on the sum of the one or more of the multiple noise signals with the transmit data signal.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 2, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hiroshi Takatori, Kofi Anim-Appiah, Hang Yan
  • Patent number: 9568163
    Abstract: A light flux controlling member (100) of the present invention has: an incident part (110) that receives light emitted from a light emitting element (210); a total reflection surface (120) that reflects a part of light incident from the incident part (110) toward a front side; a first emission part (130) that emits incident light received directly from the incident part (110) and light reflected at the total reflection surface (120) toward the outside; and a second emission part (160) that is protruded to the outside from the total reflection surface (120) and emits another part of light incident from the emission part (110) toward the outside.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 14, 2017
    Assignee: ENPLAS CORPORATION
    Inventor: Hiroshi Takatori
  • Patent number: D778332
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 7, 2017
    Assignee: ENPLAS CORPORATION
    Inventors: Yuichi Suzuki, Hiroshi Takatori
  • Patent number: D778333
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 7, 2017
    Assignee: ENPLAS CORPORATION
    Inventor: Hiroshi Takatori
  • Patent number: D778334
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 7, 2017
    Assignee: ENPLAS CORPORATION
    Inventors: Hiroshi Takatori, Yasuyuki Fukuda, Ryo Nonaka