Abstract: An information processing apparatus includes a logic circuit provided with a processing function performing a microservice, a service mesh functional circuit and a pseudo application. The logic circuit starts processing of a service that uses the request data, generates a pseudo request for a control plane communication, transmits the generated pseudo request to the pseudo application, and transmits a processing completion notification to the pseudo application based on completion of the processing of the service by the processing function. The pseudo application transmits a pseudo response to the logic circuit based on reception of the processing completion notification after reception of the pseudo request. The service mesh functional circuit rewrites destination information included in the pseudo response and transfers the pseudo response in which the destination information has been rewritten to the logic circuit.

Abstract: A communication apparatus includes a receiver configured to receive a signal from a first line, a signal processing circuit configured to perform descrambling processing on the received signal, detect a control signal from the descrambled signal, generate a signal in which an idle signal in accordance with a difference amount between a communication capacity of a second line as a transmission destination and a communication capacity of the first line is inserted in a position where the control signal is detected, and perform scrambling processing on the generated signal, and a transmitter configured to output the scrambled signal to the second line.

Abstract: A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.

Abstract: A plurality of hash values is obtained by using a plurality of hash functions based on identification information of input data. A forwarding of the input data is controlled with reference to forwarding information based on any one of the hash values. A selection of a hash value to be used for the reference based on hash management information is controlled. The hash management information indicates whether or not each of the hash values is in-use to refer the forwarding information for each hash function.

Abstract: A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.

Abstract: A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.

Abstract: In a packet relay method and device which can reduce a congestion of switching even when segment data are concentrated, segment data dividing portions respectively extract a destination address and a packet length from received packets, divide the packets into predetermined length data based on each packet length, and generates location information indicating locations in the packets respectively for the data. The segment data dividing portions add segment headers in which the location information, the destination address, and an address of its own device as a source address are set are added to each of the data, generate segment data, and provide the segment data to switches within a switch card in parallel.

Abstract: An amplifier that modulates a carrier frequency according to a digital signal and amplifies the modulated signal includes a determining portion that determines at least one of a sound quality required for the digital signal, a sound source of the digital signal, and a type of sound of the digital signal, a carrier frequency setting portion that sets a carrier frequency according to a result of the determination, and a pulse-width modulating portion that pulse-width modulates the carrier frequency according to the digital signal.

Abstract: A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Abstract: An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus.

Abstract: In a data transmission device and method provided with duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches is faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

Abstract: A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.

Abstract: A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Abstract: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

Abstract: In a data transmission device and method provided with e.g. duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches are faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.

Abstract: For restricting a scale increase of a switch device using a shared buffer, segments are received at input ports with each phase being shifted and are each composed of a predetermined length data in which each data is connected in series by a predetermined number. The segments are written in shared buffers at the same address in sequence for each segment, where the shared buffers are provided in parallel by the predetermined number. The address for each output port set in each segment is stored each time the writing is performed and the stored address is referred to in the sequence for each output port thereby to read each predetermined length data based on the address referred to from each shared buffer. Each predetermined length data read is connected in series and outputted to each output port.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.