Patents by Inventor Hiroshi Tomonaga
Hiroshi Tomonaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090257441Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.Type: ApplicationFiled: January 29, 2009Publication date: October 15, 2009Applicant: FUJITSU LIMITEDInventors: Akihiro Hata, Hiroshi Tomonaga, Katsumi Imamura
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Publication number: 20090245258Abstract: An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.Type: ApplicationFiled: March 17, 2009Publication date: October 1, 2009Applicant: FUJITSU LIMITEDInventors: Jun Tanaka, Hiroshi Tomonaga, Takashi Kuwabara, Hiroshi Kurosaki
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Publication number: 20090245104Abstract: An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus.Type: ApplicationFiled: March 16, 2009Publication date: October 1, 2009Applicant: Fujitsu LimitedInventors: Kazuto NISHIMURA, Hiroshi TOMONAGA, Akihiro HATA, Masamichi KASA
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Publication number: 20090172318Abstract: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.Type: ApplicationFiled: August 26, 2008Publication date: July 2, 2009Applicant: FUJITSU LIMITEDInventors: Hidenori Sugai, Hiroshi Tomonaga, Satoshi Nemoto
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Publication number: 20080151897Abstract: In a packet relay method and device which can reduce a congestion of switching even when segment data are concentrated, segment data dividing portions respectively extract a destination address and a packet length from received packets, divide the packets into predetermined length data based on each packet length, and generates location information indicating locations in the packets respectively for the data. The segment data dividing portions add segment headers in which the location information, the destination address, and an address of its own device as a source address are set are added to each of the data, generate segment data, and provide the segment data to switches within a switch card in parallel.Type: ApplicationFiled: December 19, 2007Publication date: June 26, 2008Applicant: FUJITSU LIMITEDInventors: Satoshi Nemoto, Hiroshi Tomonaga, Akihiro Hata
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Patent number: 7366165Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.Type: GrantFiled: February 19, 2002Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Masakatsu Nagata, Hiroshi Tomonaga, Naoki Matsuoka, Tsuguo Kato
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Patent number: 7227861Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.Type: GrantFiled: March 13, 2001Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Hiroshi Tomonaga, Masakatsu Nagata, Kenichi Kawarai, Naoki Matsuoka, Kenichi Okabe, Shiro Uriu
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Patent number: 7058751Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.Type: GrantFiled: August 30, 2001Date of Patent: June 6, 2006Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Masakatsu Nagata, Tsuguo Kato, Tetsuaki Wakabayashi
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Patent number: 7046685Abstract: A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.Type: GrantFiled: December 14, 1999Date of Patent: May 16, 2006Assignee: Fujitsu LimitedInventors: Naoki Matsuoka, Kenichi Kawarai, Hiroshi Tomonaga, Tsuguo Kato
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Patent number: 7023865Abstract: A packet switch which can cyclically use ? scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by ? scheduler sections independently performing scheduling processes is disclosed.Type: GrantFiled: August 30, 2001Date of Patent: April 4, 2006Assignee: Fujitsu LimitedInventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Patent number: 7016366Abstract: To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.Type: GrantFiled: March 20, 2001Date of Patent: March 21, 2006Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Tsuguo Kato
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Patent number: 6963577Abstract: A packet switch includes an input buffer memory unit having a logic queue corresponding to an output line, a control module for a first pointer indicating a scheduling start input line, a control module for a second pointer indicating a scheduling start output line of scheduling target outlines, a request management control module for retaining transmission request data about a desired output line, a scheduling processing module for starting a retrieval from within plural pieces of transmission request data from the output line indicated by the second pointer, and selecting an output line that is not ensured by other input lines, a packet buffer memory unit for temporarily storing a plurality of fixed-length packets and sequentially outputting the fixed-length packets, a switch unit for switching the fixed-length packets outputted from the packet buffer memory unit, and an address management unit for segmenting an address of the packet buffer memory unit into fixed-length blocks for a plurality of packets, anType: GrantFiled: August 22, 2000Date of Patent: November 8, 2005Assignee: Fujitsu LimitedInventors: Hiroshi Tomonaga, Naoki Matuoka, Kenichi Kawarai, Tsuguo Kato
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Patent number: 6947413Abstract: A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.Type: GrantFiled: August 29, 2001Date of Patent: September 20, 2005Assignee: Fujitsu LimitedInventors: Tetsuaki Wakabayashi, Kenichi Okabe, Shiro Uriu, Hiroshi Tomonaga, Naoki Matsuoka
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Patent number: 6920145Abstract: A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers.Type: GrantFiled: January 12, 2001Date of Patent: July 19, 2005Assignee: Fujitsu limitedInventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai
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Patent number: 6687225Abstract: The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR.Type: GrantFiled: October 19, 1999Date of Patent: February 3, 2004Assignee: Fujitsu LimitedInventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Naotoshi Watanabe, Yasuhiro Ooba, Hichiro Hayami
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Publication number: 20030147398Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.Type: ApplicationFiled: August 30, 2001Publication date: August 7, 2003Inventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Publication number: 20020122424Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.Type: ApplicationFiled: February 19, 2002Publication date: September 5, 2002Inventors: Kenichi Kawarai, Masakatsu Nagata, Hiroshi Tomonaga, Naoki Matsuoka, Tsuguo Kato
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Publication number: 20020110129Abstract: A scheduling method includes the steps of processing scheduling processes of all input lines according to a processing sequence in which a highest priority output line of a highest priority input line is processed with a first priority, in an environment in which a plurality of processing sequences have different scheduling targets among a plurality of input lines, and updating the highest priority input line and the highest priority output line of each input line for every scheduling cycle.Type: ApplicationFiled: October 9, 2001Publication date: August 15, 2002Inventors: Naoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
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Publication number: 20020101871Abstract: The object of the present invention is accommodating local connectionless information (data that is immediately transferred without establishing a path to a receive side), such as LAN data in a local area network, by an asynchronous transfer mode (ATM) network using a connection-oriented communication system (which makes data transfers after verifying that a path to the receive side has been established), thereby performing efficient, fast routing of connectionless information.Type: ApplicationFiled: November 14, 1997Publication date: August 1, 2002Applicant: FUJITSU LIMITEDInventors: Tadahiro TAKASE , Kazuo HAJIKANO , Takeshi KAWASAKI , Toshio SHIMOE , Tetsuo TACHIBANA , Teruaki HAGIHARA , Satoshi KAKUMA , Masami MURAYAMA , Satoshi KUROYANAGI , Hiroshi TOMONAGA , Jyoei LAMOI
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Publication number: 20020099900Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.Type: ApplicationFiled: August 31, 2001Publication date: July 25, 2002Inventors: Kenichi Kawarai, Hiroshi Tomonaga, Naoki Matsuoka, Masakatsu Nagata, Tsuguo Kato, Tetsuaki Wakabayashi