Patents by Inventor Hiroshi Umeda

Hiroshi Umeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140239203
    Abstract: A target supply device 4 may include a tank 51, formed of a metal, that holds a target material, an insulating member 62 that makes contact with at least part of the periphery of the tank 51, and a heater 58 that is separated from the tank 51 and heats the tank 51 via the insulating member 62.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 28, 2014
    Applicant: GIGAPHOTON INC.
    Inventors: Hiroshi UMEDA, Toshiyuki HIRASHITA
  • Patent number: 8809819
    Abstract: A target supply unit may include: a target storage unit for storing a target material thereinside; a target output unit having a through-hole formed therein, through which the target material stored inside the target storage unit is outputted; an electrode having a through-hole formed therein arranged to face the target output unit, the electrode being coated with an electrically conductive material at least on a part of a surface facing the target output unit; and a voltage generator for applying a voltage between the target material and the electrode.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Gigaphoton Inc.
    Inventors: Takayuki Yabu, Hiroshi Umeda, Hakaru Mizoguchi
  • Publication number: 20140209819
    Abstract: A target supply device may include a tank including a nozzle, a first electrode disposed within the tank, a first potential setting unit configured to set a potential at the first electrode to a first potential, a second electrode provided with a first through-hole and disposed so that a center axis of the nozzle is positioned within the first through-hole, a second potential setting unit configured to set a potential at the second electrode to a second potential that is different from the first potential, and a charge neutralization unit configured to neutralize a charge of the target material that passes through a first region located between the second electrode and the plasma generation region.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 31, 2014
    Applicant: GIGAPHOTON INC.
    Inventor: Hiroshi UMEDA
  • Patent number: 8785895
    Abstract: A target supply apparatus mounted in a chamber in which extreme ultraviolet light is generated by introducing a target material and a laser beam into the chamber may include a target generator having a nozzle, a first pipe configured to cover the nozzle, a cover opening provided in the first pipe to allow the target material to pass through the first pipe, and a first valve configured to open and close the cover opening.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: July 22, 2014
    Assignee: Gigaphoton Inc.
    Inventors: Hiroshi Umeda, Taku Yamazaki, Hakaru Mizoguchi, Toshihiro Nishisaka
  • Publication number: 20140138561
    Abstract: A target supply device may include a tank having a nozzle, a first electrode provided with a first through-hole, a second electrode provided with a second through-hole, a third electrode disposed within the tank, an anchoring portion configured to anchor the first electrode and the second electrode to the tank so that insulation among the nozzle, the first electrode, and the second electrode is maintained, and so that a center axis of the nozzle is positioned within the first through-hole and the second through-hole, a first projecting portion that is an integrated part of at least one of the first electrode and the second electrode and that is configured to project toward the nozzle, and a second projecting portion that is an integrated part of at least the second electrode and that is configured to project so as to be positioned between the first electrode and the second electrode.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: GIGAPHOTON INC.
    Inventors: Hiroshi UMEDA, Takashi OHARA, Osamu WAKABAYASHI
  • Publication number: 20140138560
    Abstract: A target supply device may include a tank including a nozzle, a first electrode provided with a first through-hole and disposed so that a center axis of the nozzle is positioned within the first through-hole, a second electrode that includes a main body portion provided with a second through-hole and a collection portion formed in a cylindrical shape extending in a direction from a circumferential edge of the second through-hole toward the nozzle and that is disposed so that the center axis of the nozzle is positioned within the second through-hole, a third electrode disposed within the tank, and a heating unit configured to heat the second electrode.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 22, 2014
    Applicant: GIGAPHOTON INC.
    Inventors: Hiroshi UMEDA, Osamu WAKABAYASHI
  • Publication number: 20140061512
    Abstract: A target supply device may include a receptacle for holding a liquid target material, a first electrode disposed within the receptacle, a nozzle portion provided in the receptacle, a second electrode provided with a first path and disposed facing the nozzle portion, a third electrode provided with a second path that, along with the first path, defines a trajectory of the liquid target material released from the nozzle portion, a first power source that applies a first potential that is higher than a common potential to the first electrode, a second power source that applies a second potential that is lower than the common potential to the third electrode, and a third power source that applies a third potential that is no greater than the first potential and is no less than the second potential to the second electrode.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: GIGAPHOTON INC.
    Inventor: Hiroshi UMEDA
  • Publication number: 20140008552
    Abstract: A target supply apparatus mounted in a chamber in which extreme ultraviolet light is generated by introducing a target material and a laser beam into the chamber may include a target generator having a nozzle, a first pipe configured to cover the nozzle, a cover opening provided in the first pipe to allow the target material to pass through the first pipe, and a first valve configured to open and close the cover opening.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 9, 2014
    Inventors: Hiroshi UMEDA, Taku YAMAZAKI, Hakaru MIZOGUCHI, Toshihiro NISHISAKA
  • Patent number: 8536017
    Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Kadoshima, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
  • Publication number: 20130228709
    Abstract: A target supply device includes a reservoir for storing a liquid target material, a first electrode electrically connected to the liquid target material stored in the reservoir, a nozzle having a through-hole through which the liquid target material stored in the reservoir is discharged, a first power supply for applying a first potential to the first electrode, a circuit electrically connected to the first electrode and configured to suppress a potential variation of the first electrode, a second electrode provided to face the through-hole in the nozzle, and a second power supply for applying a second potential that is different from the first potential to the second electrode.
    Type: Application
    Filed: November 29, 2012
    Publication date: September 5, 2013
    Applicant: GIGAPHOTON INC.
    Inventors: Hiroshi UMEDA, Hakaru MIZOGUCHI
  • Publication number: 20130155347
    Abstract: A liquid crystal display device includes: a display panel which includes a TFT array substrate and a CF substrate arranged as opposed to each other, and a liquid crystal held therebetween; and a front panel which is adhered to a front surface side of the display panel with a resin layer interposed therebetween. A display region of the display panel is provided with main spacers formed on the CF substrate and making contact with the TFT array substrate, and sub-spacers formed on the CF substrate and not reaching the TFT array substrate. A ratio of a total contact area of the main spacers and the TFT array substrate with respect to an area of the display region of the liquid crystal panel is equal to or smaller than 0.02%.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 20, 2013
    Inventors: Koji YONEMURA, Hiroshi UMEDA
  • Publication number: 20120241650
    Abstract: A target supply unit may include: a target storage unit for storing a target material thereinside; a target output unit having a through-hole formed therein, through which the target material stored inside the target storage unit is outputted; an electrode having a through-hole formed therein arranged to face the target output unit, the electrode being coated with an electrically conductive material at least on a part of a surface facing the target output unit; and a voltage generator for applying a voltage between the target material and the electrode.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 27, 2012
    Inventors: Takayuki YABU, Hiroshi Umeda, Hakaru Mizoguchi
  • Publication number: 20120208346
    Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 16, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru KADOSHIMA, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
  • Publication number: 20120056268
    Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 8, 2012
    Inventors: Masaharu MIZUTANI, Masaru KADOSHIMA, Takaaki KAWAHARA, Masao INOUE, Hiroshi UMEDA
  • Publication number: 20120045876
    Abstract: There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.
    Type: Application
    Filed: July 15, 2011
    Publication date: February 23, 2012
    Inventors: Takaaki KAWAHARA, Shinsuke Sakashita, Masaru Kadoshima, Hiroshi Umeda
  • Publication number: 20110284971
    Abstract: There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Inventors: Shinsuke SAKASHITA, Takaaki Kawahara, Masaru Kadoshima, Masao Inoue, Hiroshi Umeda
  • Patent number: 7863125
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Publication number: 20090263945
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 22, 2009
    Applicant: Renesas Technology Corp.,
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Patent number: 7569890
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Publication number: 20080137813
    Abstract: This invention provides a subject support device with a highly maneuverable top plate and an X-ray imaging apparatus with such subject support device. A subject support device comprises a top plate for a subject to lie on, and a pedestal base which cantilevers the top plate in a horizontally extendable manner, and a levelness maintaining unit which adjusts the posture of the pedestal base to maintain the levelness of a part for supporting the top plate. The levelness maintaining unit includes a detector which detects the levelness of the part for supporting the top plate, a control circuit which outputs a control signal according to a detection signal from the detector, and an actuator which changes the posture of the pedestal base according to a control signal from the control circuit.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 12, 2008
    Inventor: Hiroshi Umeda