Patents by Inventor Hiroshi Umeda
Hiroshi Umeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120056268Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.Type: ApplicationFiled: July 26, 2011Publication date: March 8, 2012Inventors: Masaharu MIZUTANI, Masaru KADOSHIMA, Takaaki KAWAHARA, Masao INOUE, Hiroshi UMEDA
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Publication number: 20120045876Abstract: There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.Type: ApplicationFiled: July 15, 2011Publication date: February 23, 2012Inventors: Takaaki KAWAHARA, Shinsuke Sakashita, Masaru Kadoshima, Hiroshi Umeda
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Publication number: 20110284971Abstract: There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.Type: ApplicationFiled: May 17, 2011Publication date: November 24, 2011Inventors: Shinsuke SAKASHITA, Takaaki Kawahara, Masaru Kadoshima, Masao Inoue, Hiroshi Umeda
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Patent number: 7863125Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: GrantFiled: June 26, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Publication number: 20090263945Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: Renesas Technology Corp.,Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Patent number: 7569890Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: GrantFiled: April 24, 2006Date of Patent: August 4, 2009Assignee: Renesas Technology Corp.Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Publication number: 20080137813Abstract: This invention provides a subject support device with a highly maneuverable top plate and an X-ray imaging apparatus with such subject support device. A subject support device comprises a top plate for a subject to lie on, and a pedestal base which cantilevers the top plate in a horizontally extendable manner, and a levelness maintaining unit which adjusts the posture of the pedestal base to maintain the levelness of a part for supporting the top plate. The levelness maintaining unit includes a detector which detects the levelness of the part for supporting the top plate, a control circuit which outputs a control signal according to a detection signal from the detector, and an actuator which changes the posture of the pedestal base according to a control signal from the control circuit.Type: ApplicationFiled: December 7, 2007Publication date: June 12, 2008Inventor: Hiroshi Umeda
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Patent number: 7247985Abstract: A semiconductor light-emitting device includes: a semiconductor substrate; a light-emitting layer formed on the semiconductor substrate; a current-blocking layer formed on a part of the light-emitting layer for restricting light-emission; a current-spreading layer formed on the current-blocking layer and the other part of the light-emitting layer; a front electrode formed on the current-spreading layer; and a rear electrode formed on a rear side of the semiconductor substrate. The current-blocking layer is composed of a central region and an outer region which surrounds the central region via a part of the current-spreading layer, so that a light-emitting region that appears on a front surface of the device has an annular shape. The front electrode and the central region of the current-blocking layer are opposed to each other.Type: GrantFiled: October 21, 2004Date of Patent: July 24, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazuaki Kaneko, Hiroshi Umeda, Kazuaki Sasaki, Junichi Nakamura
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Publication number: 20070052342Abstract: A light-emitting device includes a light-emitting element emitting primary light and a wavelength conversion portion absorbing a part of the primary light and emitting secondary light having a wavelength equal to or longer than the wavelength of the primary light. The wavelength conversion portion includes a plurality of green or yellow light-emitting phosphors and a plurality of red light-emitting phosphors. The green or yellow light-emitting phosphor is implemented by at least one selected from a specific europium (II)-activated silicate phosphor (A-1) and a specific cerium (III)-activated silicate phosphor (A-2). The red light-emitting phosphor is implemented by a specific europium (II)-activated nitride phosphor (B). The light-emitting device emitting white light at efficiency and color rendering property higher than in a conventional example can thus be provided.Type: ApplicationFiled: August 31, 2006Publication date: March 8, 2007Applicant: SHARP KABUSHIKI KAISHAInventors: Masatsugu Masuda, Masaaki Katoh, Kazuhiko Inoguchi, Hiroshi Umeda, Yuhichi Memida, Takashi Oouchida, Yuhsuke Fujita, Masatoshi Omoto
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Publication number: 20060273401Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: ApplicationFiled: April 24, 2006Publication date: December 7, 2006Applicant: Renesas Technology Corp.Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Publication number: 20060255712Abstract: A light emitting apparatus includes: a semiconductor light emitting element capable of emitting light of two wavelength components; and a fluorescent material section, having a fluorescent material contained therein, capable of emitting light, the light being radiated as a result of fluorescence from the fluorescent material when the fluorescent material is excited by the two wavelength components, wherein the two wavelength components and the wavelength component resulting from the fluorescence are adjusted so as to be set at an arbitrary color temperature on a characteristic curve of black-body radiation.Type: ApplicationFiled: April 19, 2006Publication date: November 16, 2006Inventors: Masatsugu Masuda, Hiroshi Umeda, Masaharu Kitano, Takashi Oouchida
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Publication number: 20060094140Abstract: A manufacturing method for a semiconductor light emitting device is provided. The method includes preparing a first wafer in which at least one semiconductor layer including the emitter layer is formed; disposing a second wafer transparent to an emission wavelength of the emitter layer on the surface of the first wafer; providing a bonding failure prevention structure to at least either the first wafer or the second wafer for preventing bonding failures of the first wafer and the second wafer; and applying compressive force to a contact face between the first wafer and the second wafer while at the same time, heating the contact face. The first and second wafers can be bonded across their entire surfaces without causing bonding failure.Type: ApplicationFiled: October 31, 2005Publication date: May 4, 2006Applicant: Sharp Kabushiki KaishaInventors: Yukari Inoguchi, Hiroshi Umeda, Takahisa Kurahashi, Nobuyuki Watanabe, Tetsuroh Murakami
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Publication number: 20050093428Abstract: A semiconductor light-emitting device includes: a semiconductor substrate; a light-emitting layer formed on the semiconductor substrate; a current-blocking layer formed on a part of the light-emitting layer for restricting light-emission; a current-spreading layer formed on the current-blocking layer and the other part of the light-emitting layer; a front electrode formed on the current-spreading layer; and a rear electrode formed on a rear side of the semiconductor substrate. The current-blocking layer is composed of a central region and an outer region which surrounds the central region via a part of the current-spreading layer, so that a light-emitting region that appears on a front surface of the device has an annular shape. The front electrode and the central region of the current-blocking layer are opposed to each other.Type: ApplicationFiled: October 21, 2004Publication date: May 5, 2005Applicant: Sharp Kabushiki KaishaInventors: Kazuaki Kaneko, Hiroshi Umeda, Kazuaki Sasaki, Junichi Nakamura
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Patent number: 6883582Abstract: To provide a monitoring system for remotely monitoring the operation of a molding apparatus or an air-flow and press molding apparatus. The monitoring systems for monitoring a molding apparatus and an airflow and press molding apparatus include sensors, a local unit, and a remote unit. The local unit transmits the signals associated with the required attributes, which are measured by the sensors, of the molding apparatus to the remote unit via the communication network. The remote unit is designed so that it receives the signals transmitted from the local unit; thereby the user can monitor the molding apparatus or the air-flow and press molding apparatus remotely at the production and operation by them.Type: GrantFiled: November 26, 2003Date of Patent: April 26, 2005Assignee: Sintokogio, Ltd.Inventors: Hironobu Amano, Yasuo Moribe, Hiroshi Umeda, Mitsuyuki Matsushita
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Patent number: 6812536Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.Type: GrantFiled: March 10, 2003Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Shuichi Ueno, Yukio Nishida, Hiroshi Umeda, Kenichi Ohto, Takashi Terauchi, Shigeru Shiratake, Akinori Kinugasa
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Publication number: 20040129404Abstract: To provide a monitoring system for remotely monitoring the operation of a molding apparatus or an air-flow and press molding apparatus. The monitoring systems for monitoring a molding apparatus and an air-flow and press molding apparatus include sensors, a local unit, and a remote unit. The local unit transmits the signals associated with the required attributes, which are measured by the sensors, of the molding apparatus to the remote unit via the communication network. The remote unit is designed so that it receives the signals transmitted from the local unit; thereby the user can monitor the molding apparatus or the air-flow and press molding apparatus remotely at the production and operation by them.Type: ApplicationFiled: November 26, 2003Publication date: July 8, 2004Applicant: SINTOKOGIO, LTD.Inventors: Hironobu Amano, Yasuo Moribe, Hiroshi Umeda, Mitsuyuki Matsushita
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Publication number: 20040046219Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.Type: ApplicationFiled: March 10, 2003Publication date: March 11, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shuichi Ueno, Yukio Nishida, Hiroshi Umeda, Kenichi Ohto, Takashi Terauchi, Shigeru Shiratake, Akinori Kinugasa
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Patent number: 6693938Abstract: A discharge circuit for pulsed laser 10 in which one connecting portion of a preionization capacitor Cpp is connected to a preionization electrode 4 and the other one connecting portion of the preionization capacitor Cpp is connected to a junction between a capacitor C2 and a magnetic switch AL2. In the discharge circuit for pulsed laser 10, a voltage Vcc of the preionization capacitor Cpp, which is charged in synchronization with the charging of the capacitor C2, increases at a time t3 earlier by a predetermined time than a start time t6 of main discharge by the main discharge electrodes 1, 2. When a voltage of the preionization electrode 4 increases to a predetermined preionization start voltage through the preionization capacitor Cpp, a main discharge gap 3 is preionized by a corona discharge caused by the preionization electrode 4 and the main discharge is caused by the main discharge electrodes 1, 2 with the main discharge gap 3 fully preionized.Type: GrantFiled: September 8, 2000Date of Patent: February 17, 2004Assignee: Komatsu Ltd.Inventors: Hiroshi Umeda, Yasufumi Kawasuji, Tetsutarou Takano
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Patent number: 6683004Abstract: There is described prevention of an increase in the thickness of an oxide film of a silicon wafer, which would otherwise be caused by eruption of gas from a CVD oxide film of another wafer during the course of a high-temperature annealing operation. A semiconductor device, which has a silicon substrate and trench isolation structures for isolating a plurality of active regions from one another, is manufactured by the steps as follows. A first and a second dielectric films are formed on the silicon substrate of one of the conductivity types. The dielectric films are removed from the areas of the silicon substrate where the trench structures are to be formed. The trench structures are formed in the uncovered areas of the silicon substrate to a predetermined depth. An oxide film is deposited into the respective trench structures by means of CVD after the oxide film has been deposited on the interior surface of the respective trench structure.Type: GrantFiled: July 11, 2000Date of Patent: January 27, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masao Inoue, Akinobu Teramoto, Hiroshi Umeda
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Publication number: 20040007756Abstract: A semiconductor device of the present invention includes: a p-type silicon substrate having a main surface; a trench formed in an element isolation region on the main surface of the p-type silicon substrate; an inner wall oxide film formed on an inner wall of the trench; an oxynitride layer formed on a surface of the inner wall oxide film; and an isolation oxide film buried into the trench. On the element isolation region, there is formed a gate electrode with a gate oxide film interposed therebetween.Type: ApplicationFiled: January 10, 2003Publication date: January 15, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Masato Nishiyama, Hiroshi Umeda