Abstract: [Problem] To provide a composition for an underlayer, which can form an underlayer having flattened surface. [Means for Solution] A composition for forming an underlayer, comprising a polymer having a repeating unit containing nitrogen and a solvent. An underlayer is formed by coating this composition on a substrate, preferably baking in an inert atmosphere, and then baking in the air containing oxygen.

Abstract: [Problem] To provide such a composition for producing a sacrifice layer as has excellent properties in both heat resistance and storage stability, and also to provide a process for producing a semiconductor device using the composition. [Solution] Disclosed is a composition for producing a sacrifice layer. The composition comprises a solvent and a polymer having a repeating unit containing a nitrogen atom with a lone pair, and contains particular transition metals only in a very low content. Also disclosed is a process using the composition as a sacrificial material for producing a semiconductor device comprising a porous material.

Abstract: [Problem] To provide a dispersion containing surface-modified silica nanoparticles highly dispersed in an organic dispersion medium and also having high transparency and storage stability. [Solution] Disclosed is a method for producing surface-modified silica nanoparticles comprising: preparing a first silica nanoparticle dispersion containing silica nanoparticles and an aqueous dispersion medium; replacing the aqueous dispersion medium in the first silica nanoparticle dispersion with an organic dispersion medium comprising at least one selected from cyclic esters or cyclic amides, to obtain a second silica nanoparticle dispersion; and mixing the second silica nanoparticle dispersion with a silane coupling agent represented by the formula (1): (each R1 is independently a hydrocarbon group of C1 to C20 and R2 is a hydrocarbon group of C1 to C3), to modify the surface of the silica nanoparticles.

Abstract: A communication apparatus includes a memory, and a processor coupled to the memory and configured to calculate, based on a bandwidth variation tendency of a calculated network bandwidth between the communication apparatus and other communication apparatus, a usable network bandwidth at a transmission time at which the other communication apparatus transmits data, determine, based on the usable network bandwidth, a size of the data to be transmitted, inform the other communication apparatus of the size of the data, and receive the data of the size from the other communication apparatus at the transmission time.

Abstract: A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.

Abstract: The present invention provides a fine pattern-forming composition enabling to form a resist pattern having high dry etching resistance, and also provides a pattern formation method using that composition. This formation method hardly causes pipe blockages in the production process. The composition is used for miniaturizing a resist pattern by fattening in a process of forming a negative resist pattern from a chemically amplified resist composition, and comprises a polymer containing a repeating unit having a hydroxyaryl group and an organic solvent not dissolving the negative resist pattern. In the formation method, the fine pattern-forming composition and the resist composition are individually cast with the same coating apparatus, so as to prevent pipe blockages.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: A non-transitory computer readable medium stores a program causing a computer to execute a process. The process includes acquiring load information indicating load applied to each of multiple relay units which are included in a network system and which connect a terminal apparatus to the network system; determining, in response to a connection request being sent, a first relay unit with lower load than a second relay unit to which the connection request is sent by the terminal apparatus, based on the acquired load information; and providing information on the determined first relay unit to the terminal apparatus.

Abstract: The present invention provides a fine pattern-forming composition enabling to form a resist pattern having high dry etching resistance, and also provides a pattern formation method using that composition. This formation method hardly causes pipe blockages in the production process. The composition is used for miniaturizing a resist pattern by fattening in a process of forming a negative resist pattern from a chemically amplified resist composition, and comprises a polymer containing a repeating unit having a hydroxyaryl group and an organic solvent not dissolving the negative resist pattern. In the formation method, the fine pattern-forming composition and the resist composition are individually cast with the same coating apparatus, so as to prevent pipe blockages.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: For adjusting a positional relationship between a specimen and a probe to measure an electric characteristic of the specimen through a contact therebetween, a base table holding a specimen table holding the specimen and a probe holder holding the probe is positioned at a first position to measure the positional relationship between the probe and the specimen at the first position, and subsequently positioned at a second position to measure the positional relationship therebetween at the second position so that the probe and the specimen are contact each other at the second position, the specimen table and the probe holder are movable with respect to each other on the base table at each of the first and second positions to adjust the positional relationship between the probe and the specimen, and a measuring accuracy at the second position is superior to a measuring accuracy at the first position.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: There is provided a variable data image generating device including a plurality of first type image generating units that execute a first rendering instruction for a distributed record and generates a first type image corresponding to the record; a first type image memory that stores the first type image corresponding to each record generated by each of the first image generating units; a distributing unit that distributes a record in variable data to each of the first type image generating units; and a document image generating unit that executes a drawing program including one or more instructions for each record in the variable data, wherein the document image generating unit generates a document image for each record by obtaining the first type image corresponding to the record from the first type image memory and laying out the obtained image in response to the first rendering instruction in the rendering program.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: An image processing device including an input section, an image storage section, a storage area reserving section, a controller, and an output section is provided. The storage area reserving section reserves, when description data input via the input section indicates that a partial image including a transmission image is to be stored, a partial image area and an entire image area at the image storage section. The color space converter performs conversion using a first output color space conversion function that converts a description color space of the description data into an output color space that includes an entire image plane and a partial image plane. The controller converts the color-space converted partial image into an output image format and writes it in the partial image area, and converts the color-space converted entire image into an output image format and writes it in the entire image area.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.