Abstract: A storage apparatus includes multiple ports communicable with a server, multiple processor cores and multiple LUs (Logical Units). For each port, a port responsible core, which is a processor core to accept an I/O request received by the port, is specified. For each LU, an LU responsible core, which is a processor core responsible for I/O, is specified. The LU responsible core may be dynamically changed. The server periodically acquires identification information about the LU responsible cores from the storage apparatus. When transmitting an I/O request, the server selects a non-cross call path, which is such a path that the LU responsible core and the port responsible core are the same processor core, from among multiple paths to an I/O destination LU, which is an LU specified by the transmission target I/O request, and transmits the transmission target I/O request via the selected path.

Abstract: A storage apparatus includes multiple ports communicable with a server, multiple processor cores and multiple LUs (Logical Units). For each port, a port responsible core, which is a processor core to accept an I/O request received by the port, is specified. For each LU, an LU responsible core, which is a processor core responsible for I/O, is specified. The LU responsible core may be dynamically changed. The server periodically acquires identification information about the LU responsible cores from the storage apparatus. When transmitting an I/O request, the server selects a non-cross call path, which is such a path that the LU responsible core and the port responsible core are the same processor core, from among multiple paths to an I/O destination LU, which is an LU specified by the transmission target I/O request, and transmits the transmission target I/O request via the selected path.

Abstract: Provided is an information processing system that communicates with a storage apparatus through a plurality of paths Pi (i=1 to n, where n is a total number of the paths), and that issues an I/O to the storage apparatus through one of the paths Pi. The information processing system sets weights Wi for the respective paths Pi; obtains an I/O issue interval di of each of the paths Pi by dividing a sum total ?Wi of the weights Wi by the weight Wi set for the path Pi; obtains I/O issue timings ti(m)of each of the paths Pi by using the following equation: ti(m)=di/C+m·di (m=0, 1, 2, . . . ) (where C is a constant); and issues the I/Os to the paths Pi in an order corresponding to the an order of the I/O issue timings ti(m) chronologically arranged.

Abstract: Provided is a method of controlling a computer system that includes: a computer; a first storage device connected to the computer via a first path and a second path; and a second storage device externally-connected to the first storage system via a third path and connected to the computer via a fourth path, the first storage device providing a first storage area to the computer, the second storage device including a second storage area corresponding to the first storage area, the method including: judging whether or not a fault has occurred in at least one of the first to fourth paths; selecting, a path used for access to the first or second storage area; and transmitting the access request for the first or second storage area by using the selected path. Accordingly, in the computer system, an application can be prevented from being stopped despite a fault in a path.

Abstract: Provided is an information processing system that communicates with a storage apparatus through a plurality of paths Pi (i=1 to n, where n is a total number of the paths), and that issues an I/O to the storage apparatus through one of the paths Pi. The information processing system sets weights Wi for the respective paths Pi; obtains an I/O issue interval di of each of the paths Pi by dividing a sum total ?Wi of the weights W by the weight Wi set for the path Pi; obtains I/O issue timings ti(m)of each of the paths Pi by using the following equation: ti(m)=di/C+m·di (m=0, 1, 2, . . . ) (where C is a constant); and issues the I/Os to the paths Pi in an order corresponding to the an order of the I/O issue timings ti(m) chronologically arranged.

Abstract: Provided is a method of controlling a computer system that includes: a computer; a first storage device connected to the computer via a first path and a second path; and a second storage device externally-connected to the first storage system via a third path and connected to the computer via a fourth path, the first storage device providing a first storage area to the computer, the second storage device including a second storage area corresponding to the first storage area, the method including: judging whether or not a fault has occurred in at least one of the first to fourth paths; selecting, a path used for access to the first or second storage area; and transmitting the access request for the first or second storage area by using the selected path. Accordingly, in the computer system, an application can be prevented from being stopped despite a fault in a path.

Abstract: Data of a plurality of master tables can be replicated in one replica table. A job to access a plurality of tables can be executed by accessing one replica table, and hence the job execution time is minimized. A correspondence is established between data using, as a key, particular data in the data of a plurality of master tables. The data field for the key is defined by the replication definition. Timing of replication for the replica table is also defined in the program to execute replication. The replication program generates, at execution thereof, the control table according to the definition and manages the operation states of a plurality of master tables and the replication state of the replica table to thereby conduct replication for the replica table at the defined timing.

Abstract: A vehicle airbag apparatus in which a frame and reinforcement members can be vibration-welded to an instrument panel with uniform strength and without distortion or discoloration of the instrument panel cover caused by the vibration welding. First weld ribs on a frame and second weld ribs on reinforcement members joined to the frame have a length which extends in the direction of vibration welding. The lengths of the first weld ribs and the second weld ribs extending in the vibration direction are set to be three times or more as long as an amplitude of the vibration welding. Passages for flowing a cooling fluid along the first weld ribs are provided on the joining surfaces of the joint flange, and furthermore, passages for flowing the cooling fluid along the second weld ribs may be provided on the joining surfaces of the reinforcements.

Abstract: The invention provides an airbag apparatus for an automobile in which a frame and reinforcement members can be vibration-welded to an instrument panel with uniform strength and the product can be prevented from being thermally deformed or discolored by heat caused by the vibration welding. First weld ribs projectedly provided on joining surfaces of an joint flange of a frame are extended long in a vibration direction of vibration welding, second weld ribs projectedly provided on joining surfaces of reinforcements of reinforcement members are extended long in the vibration direction of the vibration welding, and in particular, the lengths of the first weld ribs and the second weld ribs extending in the vibration direction are set to be three times or more as long as an amplitude of the vibration welding.

Abstract: In an information processing system comprising a storage equipment which includes a logical unit logically assigned to physical devices and an information processing apparatus which sends data input/output requests to the storage equipment, wherein the data input/output requests are transferred through logical paths serving as communication paths to the logical unit, the information processing apparatus comprises a path selection management section which manages configurations of a plurality of blocks into which the logical unit is divided, an I/O request allocation section which allocates data input/output requests to be transmitted to the storage equipment to the logical paths, and I/O processing units which transmit the data input/output requests through the logical paths, according to the allocation determined by the I/O request allocation section, pursuant to an established protocol, wherein the path selection management section assigns at least one logical path to one block.

Abstract: In an information processing system comprising a storage equipment which includes a logical unit logically assigned to physical devices and an information processing apparatus which sends data input/output requests to the storage equipment, wherein the data input/output requests are transferred through logical paths serving as communication paths to the logical unit, the information processing apparatus comprises a path selection management section which manages configurations of a plurality of blocks into which the logical unit is divided, an I/O request allocation section which allocates data input/output requests to be transmitted to the storage equipment to the logical paths, and I/O processing units which transmit the data input/output requests through the logical paths, according to the allocation determined by the I/O request allocation section, pursuant to an established protocol, wherein the path selection management section assigns at least one logical path to one block.

Abstract: A program for use in an information processing apparatus is disclosed. The apparatus has the function of displaying at a user interface a plurality of information items concerning a communication path for sending a data input/output request to a storage device. The program permits the apparatus to execute at least either one of the steps which follow: updating at least one of the information items being displayed in accordance with a present state of the communication path, and updating at least one of the information items being displayed when receiving from the user interface an input which requests updating of the information being displayed.

Abstract: Data of a plurality of master tables can be replicated in one replica table. A job to access a plurality of tables can be executed by accessing one replica table, and hence the job execution time is minimized. A correspondence is established between data using, as a key, particular data in the data of a plurality of master tables. The data field for the key is defined by the replication definition. Timing of replication for the replica table is also defined in the program to execute replication. The replication program generates, at execution thereof, the control table according to the definition and manages the operation states of a plurality of master tables and the replication state of the replica table to thereby conduct replication for the replica table at the defined timing.

Abstract: Data of a plurality of master tables can be replicated in one replica table. A job to access a plurality of tables can be executed by accessing one replica table, and hence the job execution time is minimized. A correspondence is established between data using, as a key, particular data in the data of a plurality of master tables. The data field for the key is defined by the replication definition. Timing of replication for the replica table is also defined in the program to execute replication. The replication program generates, at execution thereof, the control table according to the definition and manages the operation states of a plurality of master tables and the replication state of the replica table to thereby conduct replication for the replica table at the defined timing.

Abstract: Data of a plurality of master tables can be replicated in one replica table. A job to access a plurality of tables can be executed by accessing one replica table, and hence the job execution time is minimized. A correspondence is established between data using, as a key, particular data in the data of a plurality of master tables. The data field for the key is defined by the replication definition. Timing of replication for the replica table is also defined in the program to execute replication. The replication program generates, at execution thereof, the control table according to the definition and manages the operation states of a plurality of master tables and the replication state of the replica table to thereby conduct replication for the replica table at the defined timing.

Abstract: A microprocessor having a word data memory has a CPU data bus, an address register, an incrementer, a first byte data memory circuit, a second byte data memory circuit, a data input switching circuit and a data output switching circuit. The address register stores all the bit information of an address on the CPU data bus in response to a latching signal. The incrementer receives an address specifying signal as well as a logical product. The first byte data memory circuit provides a logical addition. The second byte data memory circuit receives an address specifying output. The data input switching circuit selectively transfers both word writing and byte writing data into the first and second byte data memory circuits. The data output switching circuit selectively transfers both word and byte data from the memory circuits to the CPU data bus.

Abstract: An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency.

Abstract: In a watchdog timer comprising a reset data detection circuit for detecting input reset data and outputting a reset signal, and a first counter that outputs a carry signal unless, before its count overflows, it receives a reset signal from said reset data detection circuit, the rest data detection circuit comprises a latch circuit for latching said reset data, a second couner for counting the number of times a said reset signal is generated, and a comparator for comparing the output data from the latch circuit and the second counter and outputting the reset signal when the output data from the latch circuit and the outputting the reset signal match.

Abstract: A data bus discharging circuit capable of enabling the high-speed operation of a microprocessor, includes a control signal generating circuit which provides control signals, a precharge/enable signal generating circuit which provides a precharge control signal and an enable signal, a discharge detecting circuit which detects small changes in the potential of the bit lines of the data bus, and a discharging circuit which sets the bit lines of the data bus selectively at a ground potential in response to the discharge detecting circuit.

Abstract: In a CMOS type input-output circuit having an input control circuit, an output control circuit, a buffer circuit, a CMOS output buffer circuit and an input buffer circuit, the input-output circuit being capable of bidirectional transmission of information between a data bus and an I/O port, improvements on the control circuit are embodied by selecting a gate circuit in the input control circuit corresponding to that in the output control circuit. The output control circuit is connected to the input control circuit and the CMOS output buffer circuit. The CMOS output buffer circuit is connected to the input control circuit and the I/O port. Upon inputting a signal to both control circuits, the output control circuit causes the CMOS output buffer circuit to be electrically floating; the input control circuit outputs a level fixing signal regardless of the logic level of the I/O port.