Patents by Inventor Hiroshi Yokouchi

Hiroshi Yokouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4680491
    Abstract: In a CMOS type input-output circuit having an input control circuit, an output control circuit, a buffer circuit, a CMOS output buffer circuit and an input buffer circuit, the input-output circuit being capable of bidirectional transmission of information between a data bus and an I/O port, improvements on the control circuit are embodied by selecting a gate circuit in the input control circuit corresponding to that in the output control circuit. The output control circuit is connected to the input control circuit and the CMOS output buffer circuit. The CMOS output buffer circuit is connected to the input control circuit and the I/O port. Upon inputting a signal to both control circuits, the output control circuit causes the CMOS output buffer circuit to be electrically floating; the input control circuit outputs a level fixing signal regardless of the logic level of the I/O port.
    Type: Grant
    Filed: May 29, 1985
    Date of Patent: July 14, 1987
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Yokouchi, Kazuhiko Miyazaki
  • Patent number: 4631665
    Abstract: In a microprocessor having a programmable logic array there are provided a program counter for designating an instruction data, a data bus line, a timing and control circuit for outputting an internal reset signal in response to an external reset signal, a programmable logic array that outputs a reset data signal and a reset data bus control signal by interpreting the reset signal as an instruction, and a gate circuit for sending the reset data signal to the data bus line in response to the reset data bus control signal to reset the program counter.
    Type: Grant
    Filed: April 5, 1983
    Date of Patent: December 23, 1986
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroshi Yokouchi
  • Patent number: 4551821
    Abstract: A data bus precharging circuit has: a charging circuit for charging a common data bus in response to a precharge control signal, the common data bus having a plurality of bit lines; a precharge sensing circuit for generating a reset signal when all of the bit lines of the data bus are charged; and a control signal generating circuit for the charging circuit to charge the data bus when a precharge clock signal is inputted to the control signal generating circuit, and for disabling the charging circuit from charging the data bus when the reset signal is inputted to the control signal generating circuit from the precharge sensing circuit.
    Type: Grant
    Filed: April 11, 1983
    Date of Patent: November 5, 1985
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Yokouchi, Ryuichi Iketani