Patents by Inventor Hiroshi Yoshida
Hiroshi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762394Abstract: A position detection apparatus comprises: a map information creation part that creates map information representing a position in a space including a floor surface on which at least one detection object may be disposed; a mask information creation part that creates mask information, by extracting a region of a predetermined height range within a height range from the floor surface when the detection object is disposed in the space from the map information; a specifying part that specifies partial optical image information, by removing a region corresponding to the mask information from the optical image information; and a detection part that specifies a positional relationship between the map information and the partial optical image information at a pixel level, and detects a position of the detection object in the map information based on the specified positional relationship.Type: GrantFiled: October 30, 2019Date of Patent: September 19, 2023Assignee: NEC CORPORATIONInventors: Shinya Yasuda, Hiroshi Yoshida
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Publication number: 20230288944Abstract: Among a plurality of transportation systems manufactured by different manufacturers, when a collision avoidance function activates with respect to a transportation device belonging to a first transportation system and a transportation device belonging to a second transportation system, the transportation time becomes longer than initially expected and the transportation efficiency decreases. A transportation system includes a first transportation device used for work involving transportation of goods, and a control device. The control device is provided with: a prediction unit for predicting, based on progress information representing the progress of work, the state of travel of a second transportation device used for the work; a determining unit for determining a travel plan for the first transportation device according to the state of travel of the second transportation device predicted by the prediction unit; and a control unit for controlling the first transportation device based on the travel plan.Type: ApplicationFiled: May 14, 2020Publication date: September 14, 2023Applicant: NBC CorpotationInventors: Taichi Kumagai, Hiroshi Yoshida, Shinya Yasuda
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Publication number: 20230287660Abstract: A work control method according to the present invention includes a construction machine control step (S1) of driving a movable part of a construction machine based on a first input value input for each process cycle that is periodically repeated; a posture detection step of detecting the position of the movable part as a posture detection value; a feedback input value computation step of computing a second input value that reduces an error between a target value of the movable part and the posture detection value; and an input value correction step of correcting a second input value by a correction amount computed based on the first input value and an estimated value of an arrival time for the movable part to reach the target value for each process cycle.Type: ApplicationFiled: July 16, 2021Publication date: September 14, 2023Applicant: NEC CorporationInventor: Hiroshi Yoshida
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Publication number: 20230281273Abstract: A reliability determination system according to an embodiment of the present disclosure includes a measurement unit, a determination unit, and a storage unit. The measurement unit measures a movement of a center of gravity of an operator who inputs data. The determination unit determines the reliability of the input data using a result of the measurement of the movement of the center of gravity of the operator inputting the data. The storage unit stores the reliability in association with the input data.Type: ApplicationFiled: June 12, 2020Publication date: September 7, 2023Inventors: Yoshiaki Shoji, Hiroshi Yoshida, Masanobu Sakamoto, Tomoko SHIBATA
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Publication number: 20230271522Abstract: A vehicle configured to perform external charging for charging an in-vehicle power storage device using electric power supplied from a system power supply outside the vehicle, wherein the vehicle includes a control device and a storage device. The control device is configured to set a command value of a charging current supplied from the system power supply to the power storage device through the charging device during the external charging, and to control the charging current by transmitting the command value to the charging device. The storage device is configured to store a program executed by the control device. The control device calculates an integrated value of the command value when the command value is larger than a threshold value. The control device is configured to execute a reduction process of reducing the command value when the integrated value is large than when the integrated value is small.Type: ApplicationFiled: December 22, 2022Publication date: August 31, 2023Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yoshiaki KIKUCHI, Hiroshi YOSHIDA, Akira KIYAMA, Yu SHIMIZU, Kensaku MIYAZAWA, Takayuki OSHINO
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Patent number: 11731531Abstract: An ECU performs processing including obtaining a full charge capacity when a cooling apparatus remains stopped, showing textual information that inquires about whether or not cooling can be carried out when a battery temperature is equal to or lower than a threshold value TB(1), when the full charge capacity is equal to or lower than a threshold value C(1), and when the battery temperature is equal to or higher than a threshold value TB(2), carrying out battery cooling control when a request for carrying out cooling has been issued, and maintaining a standstill state of the cooling apparatus when no request for carrying out cooling has been issued.Type: GrantFiled: October 16, 2020Date of Patent: August 22, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi Yoshida, Nobuyuki Tanaka, Kazuki Kubo
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Publication number: 20230260917Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a conductive body, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The conductive body is located in the first semiconductor region with an insulating part interposed. A lower surface of the conductive body includes first and second surfaces. The gate electrode is located in the insulating part. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions.Type: ApplicationFiled: July 13, 2022Publication date: August 17, 2023Inventors: Saya SHIMOMURA, Hiroaki KATOU, Yasuhiro KAWAI, Hiroshi YOSHIDA
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Publication number: 20230259840Abstract: A state detection device includes: an acquisition unit that acquires sensor values related to a center of gravity sway of a worker as time series data from a sensor which is disposed on a leg of equipment for work at height that the worker gets on and which outputs the sensor values; a calculation unit that calculates a feature of a center of gravity sway area and an evaluation value related to the center of gravity sway of the worker from the time series data; an abnormality determination unit that determines whether or not the sensor values are abnormal according to whether or not the feature of the center of gravity sway area satisfies an abnormality determination condition; and a determination unit that determines that the worker is in an unstable state if the sensor values are determined not to be abnormal and the evaluation value is equal to or greater than a threshold value.Type: ApplicationFiled: June 29, 2020Publication date: August 17, 2023Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Taisuke WAKASUGI, Tomoko SHIBATA, Hiroshi YOSHIDA, Rie SAKAI
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Publication number: 20230251138Abstract: A colorimetric apparatus includes: an opening portion that is disposed at a bottom of an apparatus main body and that introduces light arriving from a measurement target to inside the apparatus main body; an incident light processing unit that processes light incident through the opening portion; a rotor that is provided at the bottom of the apparatus main body and is in contact with the measurement target, the rotor having an elliptical shape and being driven to rotate about a rotary shaft when the apparatus main body moves in a predetermined direction; a detector that detects displacement of the rotary shaft in a direction in which the rotary shaft advances and retreats with respect to the measurement target as the rotor rotates; and a control unit that receives a signal from the incident light processing unit and the detector.Type: ApplicationFiled: February 8, 2023Publication date: August 10, 2023Inventor: Hiroshi YOSHIDA
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Publication number: 20230252378Abstract: An information processing apparatus according to one embodiment includes an assignment cost value list acquisition unit that acquires a first assignment cost value list including an assignment cost value of an individual worker of a plurality of workers for an individual task of a plurality of tasks, a constraint information acquisition unit that acquires information indicating a constraint for an assignment of the individual task, and a constraint reflection unit that generates a second assignment cost value list in accordance with a change of one or more of the assignment cost values including the first assignment cost value list in accordance with the constraint.Type: ApplicationFiled: June 12, 2020Publication date: August 10, 2023Inventors: Satoshi TAKATSU, Tomoko SHIBATA, Hiroshi YOSHIDA, Masanobu SAKAMOTO
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Patent number: 11721378Abstract: An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.Type: GrantFiled: January 31, 2023Date of Patent: August 8, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Publication number: 20230235581Abstract: A measurement system according to the present embodiment includes a work tool, a sensor unit, an acquisition unit, a change unit, and a calculation unit. The work tool has a tread board with a variable width. The sensor unit is provided in the work tool. The acquisition unit acquires, from the sensor unit, time-series data on gravity center sway of a worker, in a state where the worker is standing on the tread board. The change unit reduces the width of the tread board in response to a trigger. The calculation unit calculates, from the time-series data, an evaluation value for the gravity center sway of the worker, for each width of the tread board.Type: ApplicationFiled: June 15, 2020Publication date: July 27, 2023Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Rie SAKAI, Hiroshi YOSHIDA, Hiroshi OIWA, Tomoko SHIBATA
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Patent number: 11709210Abstract: Provided is an interlock device for a high voltage apparatus which enables not only the diagnosis of the connected or non-connected state of a connector during normal operation of the interlock device, but also the detection of a failure of the interlock device itself, including a failure of the interlock loop.Type: GrantFiled: February 14, 2020Date of Patent: July 25, 2023Assignee: SANDEN CORPORATIONInventors: Hiroshi Yoshida, Yunhai Jin
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Publication number: 20230230883Abstract: A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.Type: ApplicationFiled: July 5, 2022Publication date: July 20, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventor: Hiroshi Yoshida
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Publication number: 20230196590Abstract: A positioning method is configured to determine intra-image coordinates representing the position of a moving body in the captured image of a moving body while acquiring real-space coordinates representing the position of the moving body in real space. The intra-image coordinates of the moving body are transformed into the real-space coordinates of the moving body according to the association between the intra-image coordinates and the real-space coordinates.Type: ApplicationFiled: March 27, 2020Publication date: June 22, 2023Applicant: NEC CorporationInventors: Shinya YASUDA, Hiroshi YOSHIDA
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Publication number: 20230178134Abstract: An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.Type: ApplicationFiled: January 31, 2023Publication date: June 8, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Publication number: 20230169433Abstract: A rule processing apparatus according to an embodiment has: an evaluation unit that evaluates, by comparing a plurality of business data with a first rule used for evaluating whether business data is appropriate or not and a second rule used for evaluating whether the business data is inappropriate or not, whether or not the business data conforms to the first or second rule for each business data, and thereby evaluates whether the business data is appropriate or not; a second calculation unit that calculates the proportion of the number of business data conforming to the first or second rule to the total number of the business data and a ratio that is based on the number of business data evaluated as conforming to the first rule and the number of business data evaluated as conforming to the second rule based on an evaluation result; and a determination unit that determines that the first or second rule needs to be increased or decreased in number based on the rule hit rate and the ratio.Type: ApplicationFiled: April 30, 2020Publication date: June 1, 2023Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventor: Hiroshi YOSHIDA
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Publication number: 20230171966Abstract: A 3D monolithic stacking memory structure is provided in the present invention, including a semiconductor substrate, a field effect transistor (FET) on the semiconductor substrate, a plurality of back-end metal layers on the FET and the semiconductor substrate, an oxide-semiconductor FET (OSFET) in the back-end metal layers, wherein a drain of the OSFET is connected with a gate of the FET, and a FEMIM storage capacitor formed on the back-end metal layers, wherein a bottom electrode of the FEMIM storage capacitor is connected with the drain of the OSFET and the gate of the FET, and the FET, the OSFET and the FEMIM storage capacitor are stacked in order from bottom to top on the semiconductor substrate.Type: ApplicationFiled: March 10, 2022Publication date: June 1, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Publication number: 20230158202Abstract: Provided is a local hemostasis material, which exerts little influence on the human body, is inexpensive, and exerts a good hemostatic. The local hemostasis material comprises a base material having a first major surface and a layer including cationized cellulose on the first major surface, wherein the layer including cationized cellulose has a thickness of no less than 6.7 µm.Type: ApplicationFiled: December 25, 2020Publication date: May 25, 2023Applicants: ARTISAN LAB CO., LTD., NIPRO CORPORATIONInventors: Kazuhiko Shibata, Noriko Hattori, Hiroshi Yoshida
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Publication number: 20230154532Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.Type: ApplicationFiled: November 17, 2022Publication date: May 18, 2023Inventors: Hiroshi YOSHIDA, Toshimasa NAMEKAWA, Satoru ARAKI, Etsuo FUKUDA, Tetsuo ENDOH