Patents by Inventor Hiroshi Yoshida
Hiroshi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230132577Abstract: A filtering device is configured to estimate the characteristics of noise superposed on measurement data relating to the status of a controlled machine based on the status information representing the status of a controlled machine, thus adjusting the filtering to eliminate noise based on the estimated noise characteristics.Type: ApplicationFiled: March 30, 2020Publication date: May 4, 2023Applicant: NEC CorporationInventors: Daisuke OHTA, Hiroshi YOSHIDA, Tatsuya YOSHIMOTO
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Publication number: 20230137738Abstract: A ferroelectric memory structure including a substrate, a ferroelectric capacitor structure, and a switch device is provided. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure.Type: ApplicationFiled: November 30, 2021Publication date: May 4, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Publication number: 20230135334Abstract: An information processing device calculates multiple types of assignment cost values for realizing realistic task assignment. The information processing device includes a first assignment cost value calculation unit, a classification unit, and a second assignment cost value calculation unit. The first assignment cost value calculation unit calculates a first assignment cost value by using a first coefficient based on a first restriction in accordance with work skills of workers, on the basis of past task assignment results indicating tasks done by workers on each day. The classification unit classifies the workers based on the past task assignment results. The second assignment cost value calculation unit calculates a second assignment cost value by using a second coefficient based on a second restriction in accordance with classifications of the workers determined by the classification unit, on the basis of the past task assignment results.Type: ApplicationFiled: April 9, 2020Publication date: May 4, 2023Inventors: Satoshi TAKATSU, Tomoko SHIBATA, Hiroshi Yoshida
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Publication number: 20230127364Abstract: A cooling simulation method is a cooling simulation method for predicting a temperature change inside a heated workpiece when a coolant is brought into contact with the workpiece. In the cooling simulation method, a flow velocity of the coolant on the surface of the workpiece is calculated by a flow analysis of the coolant by a thermal fluid simulation, and the temperature change inside the workpiece is calculated based on a temperature of the surface of the workpiece and the calculated flow velocity.Type: ApplicationFiled: October 27, 2022Publication date: April 27, 2023Inventors: Takashi Horino, Hiroshi Yoshida
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Publication number: 20230118921Abstract: A monitoring device for a battery that supplies electric power to a traction motor of a vehicle includes a sensor that detects a voltage of a battery cell of the battery, and a processing circuit that executes abnormality detection processing for detecting an abnormality in the battery, based on a detected voltage value that is detected by the sensor. The processing circuit executes processing for identifying a first elapsed time from a main switch of the vehicle being turned off until charging or discharging is started between the battery and predetermined on-board equipment, processing for identifying a second elapsed time from starting of the charging or discharging between the battery and the on-board equipment to a current point in time, and the abnormality detection processing when a total time of the first elapsed time and the second elapsed time reaches a predetermined threshold value.Type: ApplicationFiled: August 16, 2022Publication date: April 20, 2023Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tsubasa MIGITA, Yoshihiro UCHIDA, Hiroshi YOSHIDA
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Patent number: 11624783Abstract: A battery diagnosis apparatus includes an SOC calculator, a ?SOC obtaining unit, a largest block identification unit, and a diagnosis unit. The SOC calculator calculates an SOC for each parallel cell block included in a battery assembly based on an output from a battery sensor that detects a state of the battery assembly. When charging or discharging of the battery assembly is carried out, the ?SOC obtaining unit obtains ?SOC for each parallel cell block. The largest block identification unit identifies a largest block in a diagnosis target. When a degree of deviation between ?SOC of the largest block and a ?SOC reference value exceeds a prescribed level, the diagnosis unit determines that abnormality has occurred in the largest block in the diagnosis target.Type: GrantFiled: January 29, 2021Date of Patent: April 11, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirotaka Ito, Hiroshi Yoshida, Yoshihiro Uchida, Tetsuya Watanabe
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Patent number: 11610621Abstract: An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.Type: GrantFiled: September 27, 2021Date of Patent: March 21, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Publication number: 20230071750Abstract: An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.Type: ApplicationFiled: September 27, 2021Publication date: March 9, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Patent number: 11600502Abstract: A substrate liquid processing apparatus includes a processing tub configured to store a processing liquid therein; a processing liquid supply configured to supply the processing liquid into the processing tub; a processing liquid drain device configured to drain the processing liquid from the processing tub; and a controller configured to control the processing liquid supply and the processing liquid drain device. The controller calculates, in response to an instruction to change a concentration of a preset component of the processing liquid stored in the processing tub, a drain amount and a feed amount of the processing liquid from/into the processing tub based on information upon a current concentration of the preset component, information upon a concentration increment thereof per unit time and information upon the changed concentration thereof, and controls the processing liquid supply and the processing liquid drain device based on the calculation result.Type: GrantFiled: August 21, 2019Date of Patent: March 7, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Hiroshi Yoshida, Yuki Ishii
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Publication number: 20230049482Abstract: A power management system including a management apparatus configured to assign divided computation processing constituting at least a part of predetermined computation processing to a distributed computing device placed in a facility, wherein the management apparatus includes a controller configured to perform assignment processing configured to assign the divided computation processing to the distributed computing device based on at least one of a prediction value of an output power of a distributed power supply placed in the facility, a prediction value of power consumption of the facility, and a prediction value of a surplus power of the facility.Type: ApplicationFiled: December 25, 2020Publication date: February 16, 2023Inventors: Kazuhide TODA, Yasuhiro NAKAMURA, Yusuke KISHINA, Noriyasu KAWAKITA, Takashi INOUE, Tomoya SHIMOMURA, Kenji IKEUCHI, Hiroshi YOSHIDA
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Publication number: 20230052914Abstract: A power management system including a management apparatus configured to assign divided computation processing constituting at least a part of predetermined computation processing to a distributed computing device placed in a facility, wherein the management apparatus includes a receiver configured to receive a message including an information element indicating executability of computation processing by the distributed computing device, and a controller configured to perform assignment processing configured to assign the divided computation processing to the distributed computing device based on the executability of the computation processing.Type: ApplicationFiled: December 25, 2020Publication date: February 16, 2023Inventors: Kazuhide TODA, Yasuhiro NAKAMURA, Yusuke KISHINA, Noriyasu KAWAKITA, Takashi INOUE, Tomoya SHIMOMURA, Kenji IKEUCHI, Hiroshi YOSHIDA
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Patent number: 11579615Abstract: A remote control apparatus performs: calculating a path and a moving speed to reach a desired destination from a current position of the control target apparatus; measuring a communication delay time between the remote control apparatus and the control target apparatus; estimating an overshoot region based on the communication delay time, a stored size of the control target apparatus, and the moving speed; predicting whether the control target apparatus will contact with a peripheral object(s), based on the path, the overshoot region, and stored peripheral object information of the control target apparatus; calculating the moving speed information to be given to the control target apparatus so that a moving direction of the control target apparatus changes by a predetermined value or more when predicted that the control target apparatus will contact with a peripheral object(s); and transmitting a control signal including the moving speed information to the control target apparatus.Type: GrantFiled: November 7, 2018Date of Patent: February 14, 2023Assignee: NEC CORPORATIONInventors: Taichi Kumagai, Hiroshi Yoshida
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Publication number: 20230042745Abstract: A level shift transistor of a first conductivity type configured to level shift a signal from a primary side circuit to a secondary side circuit between the primary side circuit having a primary side reference potential as reference and the secondary side circuit having a secondary side reference potential independent from the primary side reference potential as reference, a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit, a capacitor connected in parallel to the diode, and an inverter configured to invert the signal are provided. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, and a second main electrode thereof is connected to an output of the inverter. The inverter operates between the primary side reference potential and the primary side power supply.Type: ApplicationFiled: May 12, 2022Publication date: February 9, 2023Applicant: Mitsubishi Electric CorporationInventors: Yuta TSUKUMA, Hiroshi YOSHIDA
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Publication number: 20230038759Abstract: A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer.Type: ApplicationFiled: August 16, 2021Publication date: February 9, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Ming-Han Liao, Min-Cheng Chen, Hiroshi Yoshida
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Patent number: 11573315Abstract: According to an embodiment, a first device includes: a first transceiver configured to transmit two or more first carrier signals using an output of a first reference signal source and to receive two or more second carrier signals; and a calculation unit, and a second device includes: a second transceiver configured to transmit the two or more second carrier signals using an output of a second reference signal source that operates independently of the first reference signal source and to receive the two or more first carrier signals. A frequency group of the two or more first carrier signals and a frequency group of the two or more second carrier signals are identical or substantially identical to each other, and the calculation unit calculates the distance between the first device and the second device based on a phase detection result obtained by receiving the first and second carrier signals.Type: GrantFiled: March 6, 2020Date of Patent: February 7, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Shoji Ootaka, Takayuki Kato, Masaki Nishikawa, Hiroshi Yoshida, Katsuya Nonin, Yoshiharu Nito, Masayoshi Oshiro
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Publication number: 20230034575Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.Type: ApplicationFiled: July 28, 2021Publication date: February 2, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventor: Hiroshi Yoshida
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Publication number: 20230035099Abstract: A power management system including a management apparatus configured to assign divided computation processing constituting at least a part of predetermined computation processing to a distributed computing device placed in a facility, wherein the management apparatus includes a receiver configured to receive a message including an information element indicating a type of corresponding computation processing that the distributed computing device is capable of handling, and a controller configured to perform assignment processing to assign the divided computation processing to the distributed computing device based on the type of the corresponding computation processing.Type: ApplicationFiled: December 25, 2020Publication date: February 2, 2023Inventors: Kazuhide TODA, Yasuhiro NAKAMURA, Yusuke KISHINA, Noriyasu KAWAKITA, Takashi INOUE, Tomoya SHIMOMURA, Kenji IKEUCHI, Hiroshi YOSHIDA
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Publication number: 20230029613Abstract: A power management system including a management apparatus configured to assign divided computation processing constituting at least a part of predetermined computation processing to a distributed computing device placed in a facility, wherein the management apparatus includes a receiver configured to receive a message including an information element indicating a type of a power source configured to identify electrical power allowed as electrical power to be used by the distributed computing device, and a controller configured to perform assignment processing to assign the divided computation processing to the distributed computing device based on the type of the power source.Type: ApplicationFiled: December 25, 2020Publication date: February 2, 2023Inventors: Kazuhide TODA, Yasuhiro NAKAMURA, Yusuke KISHINA, Noriyasu KAWAKITA, Takashi INOUE, Tomoya SHIMOMURA, Kenji IKEUCHI, Hiroshi YOSHIDA
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Patent number: 11560121Abstract: A first device includes: a first reference signal source; a first transmitting/receiving unit which transmits two or more first carrier signals and receives two or more second carrier signals using an output of the first reference signal source; and a calculating unit. A second device includes: a second reference signal source configured to be operated independently from the first reference signal source; and a second transmitting/receiving unit configured to transmit two or more second carrier signals and receive two or more first carrier signals using an output of the second reference signal source. A frequency group of two or more first carrier signals and a frequency group of two or more second carrier signals differ from each other. The calculating unit calculates a distance between the first device and the second device based on a phase detection result obtained by receiving the first and second carrier signals.Type: GrantFiled: March 6, 2020Date of Patent: January 24, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Shoji Ootaka, Tsuneo Suzuki, Hiroshi Yoshida, Masaki Nishikawa, Katsuya Nonin, Takayuki Kato, Yoshiharu Nito, Masayoshi Oshiro
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Patent number: 11536824Abstract: A distance measuring apparatus according to an embodiment includes, a filter section configured to perform band limitation on a transmission signal and output the transmission signal, and to perform band limitation on a reception signal from an antenna section and output the reception signal, a distance measuring section configured to perform a distance measurement computation based on the transmission signal and the reception signal, and to obtain a delay of a signal passing through the filter section and perform calibration of the distance measurement computation, a signal interruption section configured to interrupt transmission of a signal between the filter section and the antenna section, and a control section configured to control the signal interruption section to interrupt the transmission of the signal during a period of the calibration.Type: GrantFiled: March 6, 2020Date of Patent: December 27, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Takayuki Kato, Shoji Ootaka, Tsuneo Suzuki, Masaki Nishikawa, Katsuya Nonin, Hiroshi Yoshida, Yoshiharu Nito, Masayoshi Oshiro