Patents by Inventor Hiroshi Yoshihara
Hiroshi Yoshihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12222303Abstract: A transmission type small-angle scattering device of the present invention includes a goniometer 10 including a rotation arm 11. The rotation arm 11 is freely turnable around a ?-axis extending in a horizontal direction from an origin with a vertical arrangement state of the rotation arm 11 being defined as the origin, and has a vertical arrangement structure in which an X-ray irradiation unit 20 is installed on a lower-side end portion of the rotation arm 11, and a two-dimensional X-ray detector 30 is installed on an upper-side end portion of the rotation arm 11 to form a vertical arrangement structure.Type: GrantFiled: July 31, 2023Date of Patent: February 11, 2025Assignee: RIGAKU CORPORATIONInventors: Naoki Matsushima, Kiyoshi Ogata, Sei Yoshihara, Yoshiyasu Ito, Kazuhiko Omote, Hiroshi Motono, Shigematsu Asano, Katsutaka Horada, Sensui Yasuda
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Publication number: 20240389923Abstract: A muscle relaxation monitoring device includes a stimulation output unit configured to stimulate a nerve via a stimulation electrode attached to a living body of a subject, a signal detection unit configured to detect, as an electrical signal, a physiological signal generated from a muscle in response to the stimulation to the nerve by the stimulation output unit, via a lead-out electrode attached to the living body, and a controller configured to cause the stimulation output unit to stimulate the nerve, and determine an abnormal installation cause of the lead-out electrode, based on the electrical signal detected by the signal detection unit.Type: ApplicationFiled: May 13, 2024Publication date: November 28, 2024Applicant: NIHON KOHDEN CORPORATIONInventor: Hiroshi YOSHIHARA
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Publication number: 20240312513Abstract: According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor; a second memory string including a second memory cell transistor; a first word line commonly coupled to a gate of each of the first memory cell transistor and the second memory cell transistor; and a control circuit, wherein during a first read operation of reading data from the first memory string, a threshold voltage of the first memory cell transistor is less than a first voltage, a threshold voltage of the second memory cell transistor is equal to or greater than the first voltage, and the control circuit is configured to supply a voltage equal to or less than the first voltage to the first word line.Type: ApplicationFiled: March 10, 2024Publication date: September 19, 2024Applicant: Kioxia CorporationInventors: Tomohiko ITO, Hiroshi YOSHIHARA
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Publication number: 20240130604Abstract: A processing device is provided for processing an image obtained by imaging the inside of the oral cavity for use in diagnosis of the inside of the oral cavity. The processing device includes at least one processor. The at least one processor performs processing for acquiring one or more determination images of a subject through a camera for capturing an image of the subject including at least a part of a user's oral cavity, determining a possibility of contracting a predetermined disease based on a trained determination model stored in a memory to determine the possibility of contracting the predetermined disease and the one or more acquired determination images, and outputting information indicating the determined possibility of contracting the predetermined disease.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Yuji ARIYASU, Masashi SODE, Wataru TAKAHASHI, Yoshihiro TODOROKI, Atsushi FUKUDA, Hiroshi YOSHIHARA
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Publication number: 20220401007Abstract: A muscle relaxation monitoring apparatus includes a calibration processing section. The calibration processing section is configured to: set an initial stimulation current value as a starting stimulation current value; determine, as a current value variable process, one of a first and a second current value variable process; detect, as a first peak value and a second peak value, amplitude peak values of an electric signal; and detect a stimulation current value of a maximal stimulation of a subject, based on a result of a comparison of the first peak value and the second peak value, and acquires a stimulation current value that is obtained by adding a step current value to the stimulation current value, as the stimulation current value of a supramaximal stimulation of the subject.Type: ApplicationFiled: October 23, 2020Publication date: December 22, 2022Applicants: NIHON KOHDEN CORPORATION, SHUNICHI TAKAGIInventors: Hiroshi YOSHIHARA, Shigeyoshi KITAMURA, Kazuya NAGASE, Shunji IWATA, Shunichi TAKAGI
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Publication number: 20220401008Abstract: A stimulation current value that causes the supramaximal stimulation according to a subject in the muscle relaxation state is detected. A muscle relaxation monitoring apparatus includes a calibration processing section 4 for performing a calibration process that electrically stimulates a nerve which is an observation portion of a subject, by a predetermined stimulation current value at a predetermined stimulation timing, and that acquires a stimulation current value of a supramaximal stimulation exceeding a maximal stimulation of the subject, based on an amplitude peak value of an electric signal that is based on a stimulation response of a muscle due to the electrical stimulation.Type: ApplicationFiled: October 23, 2020Publication date: December 22, 2022Applicants: NIHON KOHDEN CORPORATIONInventors: Hiroshi YOSHIHARA, Shigeyoshi KITAMURA, Kazuya NAGASE, Shunji IWATA, Shunichi TAKAGI
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Publication number: 20220323014Abstract: A body electrode unit includes a body electrode and a release sheet to which the body electrode is attached. The body electrode includes a first electrode configured to stimulate a muscle of a body, a second electrode, and a third electrode. The second electrode and the third electrode are configured to detect a physiological signal from the muscle that is stimulated by the first electrode. The body electrode also includes a first connection portion arranged between the first electrode and the second electrode, and a second connection portion arranged between the third electrode and one of the first electrode and the second electrode. The first connection portion has at least one first direction changing part configured to change a direction in which the first connection portion extends, such that at least one of a distance and an angle between the first electrode and the second electrode is adjustable.Type: ApplicationFiled: September 30, 2020Publication date: October 13, 2022Inventors: Ryugo ODAKA, Shigehiro NISHIWAKI, Hiroshi YOSHIHARA, Shunji IWATA
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Patent number: 11100961Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.Type: GrantFiled: September 4, 2020Date of Patent: August 24, 2021Assignee: KIOXIA CORPORATIONInventors: Hiroshi Yoshihara, Tetsuya Amano
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Publication number: 20210128008Abstract: A muscle relaxation monitoring apparatus includes: a stimulating circuit that stimulates a nerve of a living body; a signal detecting circuit that detects an electric signal generated by a muscle reacting to the stimulation performed by the stimulating circuit; a reaction time calculating circuit that calculates a reaction time which elapses from the stimulation of the nerve by the stimulating circuit until the electric signal is detected by the signal detecting circuit; and a relaxation degree determining circuit that determines a muscle relaxation degree of the living body based on the length of the reaction time calculated by the reaction time calculating circuit.Type: ApplicationFiled: October 21, 2020Publication date: May 6, 2021Applicants: NIHON KOHDEN CORPORATION, Shunichi TAKAGI, KAWASAKI GAKUEN EDUCATIONAL FOUNDATIONInventors: Hiroshi YOSHIHARA, Shigeyoshi KITAMURA, Kazuya NAGASE, Shunji IWATA, Shunichi TAKAGI, Hideki NAKATSUKA
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Publication number: 20200402548Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Hiroshi YOSHIHARA, Tetsuya AMANO
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Patent number: 10796732Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.Type: GrantFiled: August 27, 2019Date of Patent: October 6, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Yoshihara, Tetsuya Amano
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Publication number: 20200202903Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.Type: ApplicationFiled: August 27, 2019Publication date: June 25, 2020Inventors: Hiroshi YOSHIHARA, Tetsuya AMANO
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Patent number: 8780609Abstract: A variable-resistance memory device includes a memory array section including a main memory cell employing a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element, and a reference cell section including a reference cell provided with a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element and generating a reference current used for recognizing data of the main memory cell. The direction of an applied current serving as the reference current is set in accordance with the resistance state of the reference cell.Type: GrantFiled: July 17, 2012Date of Patent: July 15, 2014Assignee: Sony CorporationInventors: Hironobu Mori, Hiroshi Yoshihara
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Patent number: 8638616Abstract: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes.Type: GrantFiled: January 19, 2011Date of Patent: January 28, 2014Assignee: Sony CorporationInventors: Hiroshi Yoshihara, Takayuki Arima, Takeshi Etou
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Patent number: 8576608Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: GrantFiled: December 5, 2011Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata
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Patent number: 8559253Abstract: A variable-resistance memory device that includes a memory-cell array employing a plurality of memory cells each including a storage element and an access transistor. The storage element has a resistance varying in accordance with the direction of a voltage applied to the storage element and the access transistor is connected in series to the storage element between a bit line and a source line. A voltage supplying circuit sets a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line.Type: GrantFiled: July 8, 2011Date of Patent: October 15, 2013Assignee: Sony CorporationInventors: Makoto Kitagawa, Hiroshi Yoshihara
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Patent number: 8411327Abstract: There is provided a data processing device that includes an obtaining unit that obtains a first image data set, a second image data set generated by reading an image formed using the first image data set, and a property data set indicating the properties of a recording medium on which the image is to be reproduced. The data processing device also includes a specifying unit that determines a threshold for a density difference between the first image data set and the second image data set, wherein the threshold depends on the property data set. The specifying unit also determines an error area where the density difference between images expressed by the first and second image data sets is equal to or greater than the threshold.Type: GrantFiled: March 21, 2008Date of Patent: April 2, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Shigekazu Yamagishi, Hirofumi Ishii, Tohru Yamano, Yosuke Takebe, Hiroshi Yoshihara
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Publication number: 20130051122Abstract: A variable-resistance memory device includes a memory array section including a main memory cell employing a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element, and a reference cell section including a reference cell provided with a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element and generating a reference current used for recognizing data of the main memory cell. The direction of an applied current serving as the reference current is set in accordance with the resistance state of the reference cell.Type: ApplicationFiled: July 17, 2012Publication date: February 28, 2013Applicant: Sony CorporationInventors: Hironobu Mori, Hiroshi Yoshihara
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Patent number: 8379430Abstract: A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.Type: GrantFiled: October 19, 2010Date of Patent: February 19, 2013Assignee: Sony CorporationInventors: Makoto Kitagawa, Tsunenori Shiimoto, Hiroshi Yoshihara
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Publication number: 20120212994Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: ApplicationFiled: December 5, 2011Publication date: August 23, 2012Applicant: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata