Abstract: A processing device is provided for processing an image obtained by imaging the inside of the oral cavity for use in diagnosis of the inside of the oral cavity. The processing device includes at least one processor. The at least one processor performs processing for acquiring one or more determination images of a subject through a camera for capturing an image of the subject including at least a part of a user's oral cavity, determining a possibility of contracting a predetermined disease based on a trained determination model stored in a memory to determine the possibility of contracting the predetermined disease and the one or more acquired determination images, and outputting information indicating the determined possibility of contracting the predetermined disease.

Abstract: A muscle relaxation monitoring apparatus includes a calibration processing section. The calibration processing section is configured to: set an initial stimulation current value as a starting stimulation current value; determine, as a current value variable process, one of a first and a second current value variable process; detect, as a first peak value and a second peak value, amplitude peak values of an electric signal; and detect a stimulation current value of a maximal stimulation of a subject, based on a result of a comparison of the first peak value and the second peak value, and acquires a stimulation current value that is obtained by adding a step current value to the stimulation current value, as the stimulation current value of a supramaximal stimulation of the subject.

Abstract: A stimulation current value that causes the supramaximal stimulation according to a subject in the muscle relaxation state is detected. A muscle relaxation monitoring apparatus includes a calibration processing section 4 for performing a calibration process that electrically stimulates a nerve which is an observation portion of a subject, by a predetermined stimulation current value at a predetermined stimulation timing, and that acquires a stimulation current value of a supramaximal stimulation exceeding a maximal stimulation of the subject, based on an amplitude peak value of an electric signal that is based on a stimulation response of a muscle due to the electrical stimulation.

Abstract: A body electrode unit includes a body electrode and a release sheet to which the body electrode is attached. The body electrode includes a first electrode configured to stimulate a muscle of a body, a second electrode, and a third electrode. The second electrode and the third electrode are configured to detect a physiological signal from the muscle that is stimulated by the first electrode. The body electrode also includes a first connection portion arranged between the first electrode and the second electrode, and a second connection portion arranged between the third electrode and one of the first electrode and the second electrode. The first connection portion has at least one first direction changing part configured to change a direction in which the first connection portion extends, such that at least one of a distance and an angle between the first electrode and the second electrode is adjustable.

Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

Abstract: A muscle relaxation monitoring apparatus includes: a stimulating circuit that stimulates a nerve of a living body; a signal detecting circuit that detects an electric signal generated by a muscle reacting to the stimulation performed by the stimulating circuit; a reaction time calculating circuit that calculates a reaction time which elapses from the stimulation of the nerve by the stimulating circuit until the electric signal is detected by the signal detecting circuit; and a relaxation degree determining circuit that determines a muscle relaxation degree of the living body based on the length of the reaction time calculated by the reaction time calculating circuit.

Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.

Abstract: A variable-resistance memory device includes a memory array section including a main memory cell employing a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element, and a reference cell section including a reference cell provided with a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element and generating a reference current used for recognizing data of the main memory cell. The direction of an applied current serving as the reference current is set in accordance with the resistance state of the reference cell.

Abstract: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes.

Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

Abstract: A variable-resistance memory device that includes a memory-cell array employing a plurality of memory cells each including a storage element and an access transistor. The storage element has a resistance varying in accordance with the direction of a voltage applied to the storage element and the access transistor is connected in series to the storage element between a bit line and a source line. A voltage supplying circuit sets a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line.

Abstract: There is provided a data processing device that includes an obtaining unit that obtains a first image data set, a second image data set generated by reading an image formed using the first image data set, and a property data set indicating the properties of a recording medium on which the image is to be reproduced. The data processing device also includes a specifying unit that determines a threshold for a density difference between the first image data set and the second image data set, wherein the threshold depends on the property data set. The specifying unit also determines an error area where the density difference between images expressed by the first and second image data sets is equal to or greater than the threshold.

Abstract: A variable-resistance memory device includes a memory array section including a main memory cell employing a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element, and a reference cell section including a reference cell provided with a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element and generating a reference current used for recognizing data of the main memory cell. The direction of an applied current serving as the reference current is set in accordance with the resistance state of the reference cell.

Abstract: A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.

Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

Abstract: Disclosed herein is a variable-resistance memory device including: a memory-cell array employing a plurality of memory cells each including a storage element having a resistance varying in accordance with the direction of a voltage applied to the storage element and including an access transistor connected in series to the storage element between a bit line and a source line; and a voltage supplying circuit for setting a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line.

Abstract: A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines.

Abstract: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes.