Abstract: A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step.

Abstract: A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.

Abstract: A thin attachment cap capable of simply taking out contents from a container containing drinking water, juice, powder or the like. In the attachment cap (30), by pressing down a pressing part (33) in the direction of an arrow (34) while a lid (31) is closed, the lid (31) rotates in the direction of an arrow (35) and an extraction port (37) is opened. When the pressing part (33) is completely pressed down, the lid (31) stands up approximately at the right angle with respect to a cap base (32). When the lid (31) stands up, the lid (31) is temporarily fixed, and a liquid or the like in the container can be smoothly taken out through the extraction port (37).

Abstract: Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method including: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Abstract: A hinge cap (10) fitted to a slant opening wall (26), which is provided around the opening of a hinge cap body (12), by means of two adjacently standing slant plugs (30, 32) of a lid (12). Because the slant plugs (30, 32) of the lid (12) are fitted by a large contact area to the slant opening wall (26) of the hinge cap body (12), the slant plugs can be applied to the hinge cap (10) having a relatively large area. Also, with the lid extended, the wall height of the slant outer plug (32) decreases as it approaches the rotation axis of the lid (12) and the wall height of the slant inner plug (30) decreases as it is away from the rotating shaft of the lid (12), so that the lid (12) can be smoothly rotated and opened in pressing and opening operation.

Abstract: A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upon the stored test vector by a vector data generator within the vector data engine to update the stored test vector; and repeating the steps of transmitting and performing so as to continuously transmit continuously changing stored test vectors to the memory array.

Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.

Abstract: Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method comprising: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.

Abstract: There is provided a data processing device comprising: an obtaining unit that obtains a first image data set, a second image data set, and a property data set, the second image data set being generated by reading an image which is formed on a recording medium in accordance with the first image data set by an image forming device, and the property data set indicating a property of the recording medium; and a specifying unit that determines a threshold for a density difference between the first image data set and the second image data set, depending on the property data set, and specifies, as an error area, an area where the density difference between images expressed by the first and second image data sets is equal to or greater than the threshold.

Abstract: A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step.

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract: A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upon the stored test vector by a vector data generator within the vector data engine to update the stored test vector; and repeating the steps of transmitting and performing so as to continuously transmit continuously changing stored test vectors to the memory array.

Abstract: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Abstract: Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.

Abstract: A lid opening mechanism in which a lid can be opened and closed on a hinge with respect to an associated body 1, includes two slits formed in an arbitrary part of the hinge 3 so as to extend along the opening/closing dimension of the hinge 3 and spaced apart from each other so as to define therebetween a pushing operation section that is large enough to be pushed with a finger, wherein the slits extend across hinge grooves of the hinge, with at least one end of each slit reaching the body or the lid, whereby it is possible for the lid of various cases, containers, etc. or the opening member of various apparatuses to be opened to a desired angle with one hand and by a one-push operation.

Abstract: A process for producing 5-amino-3-methylpyrazole which comprises reacting hydrazine with a reaction intermediate containing at least one compound selected from the group consisting of 3-chloro-3-butenonitrile and 2,3-butadienenitrile, which intermediate is obtainable from 2,3-dichloropropene and hydrocyanic acid.A process for producing 5-amino-4-chloro-3-methylpyrazole which comprises chlorinating 5-amino-3-methylpyrazole obtainable by the above-mentioned reaction, in the presence of hydrochloric acid.

Abstract: An apparel structure based on the movement of muscles during movement of the body, and a process for making such apparel, includes an apparel structure constructed to be comfortable and to have excellent adaptability to movement without tension or slack. It also provides excellent shaping-up effect, can be applied to various kinds of apparel and is particularly suitable for female underwear and shaping-up wear. It is suitable particularly for working wear, sportswear, leisure wear, etc., in which the extent of movement of the body is large, irrespective of male or female.