Abstract: A memory cell of an SRAM includes an access transistor, and an MIS switching diode. The access transistor has a drain electrode connected to a bit line of a corresponding column, a source electrode connected to a storage node, and a gate electrode connected to a word line of a corresponding row. The threshold voltage of the access transistor is small than the threshold voltage of a bit line load transistor. The MIS switching diode is connected between the storage node and a second power supply potential node. The switching initiate voltage of the MIS switching diode is greater than the difference between the first potential and the threshold voltage of the bit line load transistor, and smaller than the difference between the first potential and the threshold voltage of the access transistor. Thus, data can be read/written and held accurately.

Abstract: A memory cell includes a read/write word line R/WL1 driving access transistor Q1 in read and write operations and a write word line WL1 driving access transistor Q2 in the write operation. In the write operation, both access transistors Q1 and Q2 are driven, and storage information is written in the memory cell by a bit line and a /bit line having potentials complementary to each other. On the other hand, in the read operation, only access transistor Q1 is rendered conductive, and storage information is read out through the bit line. Since access transistor Q2 is rendered non-conductive, a P type TFT transistor and an N type transistor operate as a CMOS type inverter having a large voltage gain. Therefore, a sufficient operating margin is secured even in the read operation.

Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: A memory cell of an SRAM prevents imbalance between GND potentials of a pair of driver transistors. In the memory cell, the driver transistors Q.sub.1 and Q.sub.2 in a pair have the common source region.

Abstract: A semiconductor device includes a gate electrode, and a semiconductor layer formed on the main surface of the gate electrode with a gate oxide film therebetween. The semiconductor layer has a channel region opposing the main surface of gate electrode and source/drain regions having the channel region therebetween, and is formed so that the bent angle in the vicinity of the boundaries of the channel region and the source/drain regions is beyond 90.degree.. Thus, the semiconductor layer formed in a thin film transistor has no orthogonal bent, and, therefore the concentration of electric fields is suppressed, improving the performance of the thin film transistor.

Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

Abstract: A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

Abstract: The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors, and a pair of load transistors. The gate insulating film of access transistor is formed of a single layer of silicon oxide film, while the gate insulating film of driver transistor is formed of a stacked layer formed of a silicon oxide film and a silicon nitride film. The pair of load transistors are formed of two layers of polycrystalline silicon layers stacked upon each other with an insulating film therebetween. A source region and a drain region are formed in each of polycrystalline silicon layers with each channel region therebetween. One drain region forms a gate opposite to the other channel region, while the other drain region forms a gate opposite to the one channel region.

Abstract: A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

Abstract: An object of the present invention is to miniaturize a structure of a memory cell in an SRAM. The memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors and a pair of load transistors. The six transistors are thin film transistors. A plurality of thin film transistors are provided on a surface of a silicon substrate, forming a plurality of layers with an interlayer insulating layer interposed therebetween.

Abstract: Two resistors are connected in series between an input bonding electrode and an internal circuit, and respective conducting terminals of a first bipolar transistor are connected between the two resistors and a GND bonding electrode which is connected to the internal circuit. Respective conducting terminals of a second bipolar transistor are connected between the two resistors and a V.sub.DD bonding electrode which is connected to the internal circuit. Control terminals of the respective ones of the first and second bipolar transistors are connected to the GND bonding electrode respectively.