Patents by Inventor Hirotaka Hamamura

Hirotaka Hamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027920
    Abstract: To provide a magnetic tunnel junction (MTJ) element that is adapted to suppress the degradation of magnetic properties of a magnetic tunnel junction layer due to plasma CVD layer formation and adapted for miniaturization. The MTJ element includes a magnetic tunnel junction layer (101, 102, 103) and a plurality of passivation layers formed on a side wall of the magnetic tunnel junction layer. The plurality of passivation layers are SiN layers formed under different plasma CVD layer forming conditions and include a first passivation layer 109 formed in direct contact with the magnetic tunnel junction layer. A hydrogen ion density or hydrogen ion energy of a layer forming condition for the first passivation layer is lower than a hydrogen ion density or hydrogen ion energy of a layer forming condition for the other of the plural passivation layers. The other passivation layers include a passivation layer, a nitrogen density of which is higher than a nitrogen density of the first passivation layer.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 23, 2020
    Inventors: Katsuya MIURA, Hirotaka HAMAMURA, Yu ZHAO, Masaki YAMADA, Kiyohiko SATO
  • Publication number: 20200006644
    Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.
    Type: Application
    Filed: January 7, 2019
    Publication date: January 2, 2020
    Inventors: Yu ZHAO, Katsuya MIURA, Hirotaka HAMAMURA, Masaki Yamada, Kiyohiko SATO
  • Publication number: 20190051819
    Abstract: A magnetic tunnel junction device includes a first ferromagnetic layer, a tunnel barrier that is in contact with the first ferromagnetic layer, and a synthetic ferrimagnetic reference layer that is in contact with the tunnel barrier while being in the other side of the first ferromagnetic layer, in which the synthetic ferrimagnetic reference layer includes a second ferromagnetic layer that has a first magnetization direction while being in contact with the tunnel barrier, a magnetic layer that has a second magnetization direction which is anti-parallel to the first magnetization direction, and a first nonmagnetic layer that is interposed between the second ferromagnetic layer and the magnetic layer, and lateral dimensions of the magnetic layer of the synthetic ferrimagnetic reference layer are made larger than lateral dimensions of the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Application
    Filed: February 27, 2018
    Publication date: February 14, 2019
    Inventors: Katsuya MIURA, Masaki YAMADA, Hirotaka HAMAMURA
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10032871
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 9714262
    Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 25, 2017
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shuichiro Adachi, Masato Yoshida, Takeshi Nojiri, Yasushi Kurata, Tooru Tanaka, Akihiro Orita, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Patent number: 9673339
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 6, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
  • Patent number: 9570601
    Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: February 14, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Mori, Toshiyuki Mine, Hiroshi Miki, Mieko Matsumura, Hirotaka Hamamura
  • Patent number: 9508611
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Hirotaka Hamamura, Toshiyuki Ohno, Hiroyuki Okino, Yuki Mori
  • Publication number: 20160211389
    Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 21, 2016
    Inventors: Tooru TANAKA, Masato YOSHIDA, Takeshi NOJIRI, Yasushi KURATA, Akihiro ORITA, Shuichiro ADACHI, Tsuyoshi HAYASAKA, Takashi HATTORI, Mieko MATSUMURA, Keiji WATANABE, Masatoshi MORISHITA, Hirotaka HAMAMURA
  • Publication number: 20160190020
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Application
    Filed: August 14, 2013
    Publication date: June 30, 2016
    Inventors: Yoshinobu KIMURA, Natsuki TSUNO, Hiroya OHTA, Renichi YAMADA, Hirotaka HAMAMURA, Toshiyuki OHNO, Hiroyuki OKINO, Yuki MORI
  • Publication number: 20160149025
    Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.
    Type: Application
    Filed: July 16, 2013
    Publication date: May 26, 2016
    Inventors: Yuki MORI, Toshiyuki MINE, Hiroshi MIKI, Mieko MATSUMURA, HIrotaka HAMAMURA
  • Publication number: 20160111499
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Application
    Filed: March 29, 2013
    Publication date: April 21, 2016
    Inventors: Digh HISAMOTO, Keisuke KOBAYASHI, Naoki TEGA, Toshiyuki OHNO, Hirotaka HAMAMURA, Mieko MATSUMURA
  • Patent number: 9318558
    Abstract: The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 19, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
  • Publication number: 20150372151
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 24, 2015
    Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
  • Patent number: 9214516
    Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 15, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
  • Patent number: 9117836
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
  • Publication number: 20150228812
    Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 13, 2015
    Inventors: Tooru Tanaka, Masato Yoshida, Takeshi Nojira, Yasushi Kurata, Akihiro Orita, Shuichiro Adachi, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Publication number: 20150214391
    Abstract: A passivation film includes aluminum oxide and niobium oxide, and the passivation film is used in a photovoltaic cell element having a silicon substrate. A photovoltaic cell element includes: a p-type silicon substrate 1 that comprises monocrystalline silicon or polycrystalline silicon; an n-type impurity diffusion layer 2 that is formed on a light receiving surface of the silicon substrate 1; a first electrode 5 that is formed on the n-type impurity diffusion layer 2; a second electrode 6 that is formed on the back surface of the silicon substrate 1; a passivation film 7 that is formed on the back surface of the silicon substrate 1, the passivation film 7 having plural openings OA and including aluminum oxide and niobium oxide. The second electrode 6 is electrically connected to the back surface of the silicon substrate 1 through the plural openings OA.
    Type: Application
    Filed: July 19, 2013
    Publication date: July 30, 2015
    Inventors: Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Publication number: 20150179744
    Abstract: The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.
    Type: Application
    Filed: July 9, 2012
    Publication date: June 25, 2015
    Applicant: HITACHI , LTD.
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura