Patents by Inventor Hirotaka Hamamura

Hirotaka Hamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150372151
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 24, 2015
    Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
  • Patent number: 9214516
    Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 15, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
  • Patent number: 9117836
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
  • Publication number: 20150228812
    Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 13, 2015
    Inventors: Tooru Tanaka, Masato Yoshida, Takeshi Nojira, Yasushi Kurata, Akihiro Orita, Shuichiro Adachi, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Publication number: 20150214391
    Abstract: A passivation film includes aluminum oxide and niobium oxide, and the passivation film is used in a photovoltaic cell element having a silicon substrate. A photovoltaic cell element includes: a p-type silicon substrate 1 that comprises monocrystalline silicon or polycrystalline silicon; an n-type impurity diffusion layer 2 that is formed on a light receiving surface of the silicon substrate 1; a first electrode 5 that is formed on the n-type impurity diffusion layer 2; a second electrode 6 that is formed on the back surface of the silicon substrate 1; a passivation film 7 that is formed on the back surface of the silicon substrate 1, the passivation film 7 having plural openings OA and including aluminum oxide and niobium oxide. The second electrode 6 is electrically connected to the back surface of the silicon substrate 1 through the plural openings OA.
    Type: Application
    Filed: July 19, 2013
    Publication date: July 30, 2015
    Inventors: Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Publication number: 20150179744
    Abstract: The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.
    Type: Application
    Filed: July 9, 2012
    Publication date: June 25, 2015
    Applicant: HITACHI , LTD.
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
  • Publication number: 20150166582
    Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: July 19, 2013
    Publication date: June 18, 2015
    Inventors: Shuichiro Adachi, Masato Yoshida, Takeshi Nojiri, Yasushi Kurata, Tooru Tanaka, Akihiro Orita, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Patent number: 9000448
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Publication number: 20150044840
    Abstract: In order to provide a method for producing a SiC-MOSFET capable of increasing Vth without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.
    Type: Application
    Filed: March 30, 2012
    Publication date: February 12, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Keisuke Kobayashi, Toshiyuki Mine, Hirotaka Hamamura
  • Publication number: 20140327066
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p|-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Application
    Filed: July 18, 2014
    Publication date: November 6, 2014
    Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
  • Patent number: 8816426
    Abstract: In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: August 26, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
  • Publication number: 20140217422
    Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.
    Type: Application
    Filed: March 30, 2012
    Publication date: August 7, 2014
    Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
  • Publication number: 20130341711
    Abstract: A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 26, 2013
    Inventors: Daisuke Matsumoto, Toshiyuki Ohno, Hirotaka Hamamura
  • Publication number: 20130234163
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Application
    Filed: March 29, 2011
    Publication date: September 12, 2013
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Publication number: 20130234236
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Application
    Filed: March 17, 2013
    Publication date: September 12, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
  • Patent number: 8410543
    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
  • Publication number: 20120280369
    Abstract: There is provided a method for manufacturing a semiconductor device, comprising simultaneously or alternately exposing a substrate, which has two or more kinds of thin films having different elemental components laminated or exposed; and performing different modification treatments to the thin films respectively.
    Type: Application
    Filed: December 15, 2010
    Publication date: November 8, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsuyuki Saito, Kazuhiro Yuasa, Yoshiro Hirose, Yuji Takebayashi, Ryota Sasajima, Katsuhiko Yamamoto, Hirohisa Yamazaki, Shintaro Kogura, Hirotaka Hamamura
  • Publication number: 20120217513
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Application
    Filed: January 12, 2012
    Publication date: August 30, 2012
    Inventors: Naoki TEGA, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
  • Patent number: 8084315
    Abstract: A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a non-volatile semiconductor memory device is provided capable of enhancing the film quality of a silicon oxide film even when a silicon oxide film as a first potential barrier film is formed with a plasma oxidation method to improve the memory retention characteristics of the non-volatile memory. After a silicon oxide film, which is a main component of a first potential barrier film, is formed with a plasma oxidation method, plasma nitridation at a high temperature and a heat treatment in an atmosphere containing nitric oxide are performed in combination, thereby forming a silicon oxynitride film on the surface of the silicon oxide film, and segregating nitrogen to an interface between the silicon oxide film and a semiconductor substrate.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: December 27, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Katsuhiko Yamamoto, Tadashi Terasaki, Yoshiki Yonamoto, Hirotaka Hamamura
  • Patent number: 7863134
    Abstract: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hirotaka Hamamura, Itaru Yanagi, Toshiyuki Mine