Patents by Inventor Hirotaka Miyamoto

Hirotaka Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080296624
    Abstract: The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.
    Type: Application
    Filed: May 23, 2008
    Publication date: December 4, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Keiichi MURAYAMA, Akiyoshi TAMURA, Hirotaka MIYAMOTO, Kenichi MIYAJIMA
  • Patent number: 7449729
    Abstract: On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: November 11, 2008
    Assignee: Panasonic Corporation
    Inventors: Kenichi Miyajima, Keiichi Murayama, Hirotaka Miyamoto
  • Publication number: 20080176391
    Abstract: The present invention has an object of providing a method for manufacturing a semiconductor device which can prevent occurrence of pattern abnormality of an electrode and deterioration of an electronic property. The method for manufacturing the semiconductor device including a GaAs substrate with a portion made of GaAs includes: forming a Ti/Pt/Au/Ti electrode on the GaAs substrate, the electrode including Pt and having a layered structure in which a top layer made of Ti; forming a collector electrode including AuGe on a portion made of GaAs; and performing heat treatment on the collector electrode in a state where both of the Ti/Pt/Au/Ti electrode and the collector electrode are exposed to a surface.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 24, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hirotaka MIYAMOTO, Akiyoshi TAMURA, Keiichi MURAYAMA, Kenichi MIYAJIMA
  • Publication number: 20080088020
    Abstract: Provided is a semiconductor device and a manufacturing method of the same which improve adhesion of a semiconductor substrate to a metal wire, the semiconductor substrate having a via hole formed from a bottom surface of the semiconductor substrate up to the metal wire on a top surface of the semiconductor substrate, and the metal wire being positioned on the top surface of the semiconductor substrate where there is an opening formed since the via hole is formed. The semiconductor device includes: a metal layer formed on a semiconductor substrate; an alloy reaction layer formed below the metal layer as a result of an alloy reaction between the semiconductor substrate and the metal layer; and a via hole formed from a bottom surface side of the semiconductor substrate up to the metal layer or up to the alloy reaction layer.
    Type: Application
    Filed: July 9, 2007
    Publication date: April 17, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kenichi MIYAJIMA, Keiichi MURAYAMA, Hirotaka MIYAMOTO, Akiyoshi TAMURA
  • Publication number: 20080089209
    Abstract: An optical disc apparatus and a focus position control method can highly accurately record recording marks representing information on or reproduce such recording marks from an optical disc. A blue light beam is irradiated onto the target depth to be irradiated by driving an objective lens to focus a red light beam in a reflection/transmission film formed in the optical disc and displacing a movable lens, which is a focus moving section, of a relay lens. A blue light reflection region is formed as part of the reflection/transmission film and the position of the blue light reflection region where the red light focus and the blue light focus are aligned is defined as reference position. The movable lens is displaced by an arbitrarily selected quantity from the reference position according to the target depth.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 17, 2008
    Applicant: Sony Corporation
    Inventors: Hirotaka Miyamoto, Kimihiro Saito
  • Publication number: 20080068942
    Abstract: An optical disk apparatus irradiates first and second lights, which are emitted from an identical light source, on a disk-like volumetric recording medium from both sides thereof with first and second object lenses corresponding to the first and second lights, respectively, such that the lights are focused in an identical focal point position and records a standing wave. The optical disk apparatus includes an aberration adding unit that adds complementary aberrations to the first and second lights made incident on the volumetric recording medium, respectively.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 20, 2008
    Applicant: Sony Corporation
    Inventors: Kimihiro SAITO, Takao Kondo, Hirotaka Miyamoto
  • Publication number: 20070145412
    Abstract: The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and hi
    Type: Application
    Filed: December 21, 2006
    Publication date: June 28, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Keiichi MURAYAMA, Akiyoshi TAMURA, Hirotaka MIYAMOTO, Kenichi MIYAJIMA
  • Publication number: 20070012949
    Abstract: A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 18, 2007
    Inventors: Katsuhiko Kawashima, Masahiro Maeda, Keiichi Murayama, Hirotaka Miyamoto
  • Publication number: 20060289896
    Abstract: A semiconductor device has an interconnect layer for providing an electric connection between a base electrode and a base terminal provided on the region of a semi-insulating substrate on which a transistor is not formed. A resistor layer composed of a material different from respective materials composing the base electrode and the interconnect layer is formed on the base electrode and the base electrode and the interconnect layer are connected to each other via the resistor layer.
    Type: Application
    Filed: February 7, 2006
    Publication date: December 28, 2006
    Inventors: Hirotaka Miyamoto, Keiichi Murayama, Kenichi Miyajima
  • Publication number: 20060237743
    Abstract: On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 26, 2006
    Inventors: Kenichi Miyajima, Keiichi Murayama, Hirotaka Miyamoto
  • Publication number: 20060132241
    Abstract: There are provided a transistor integrated circuit device which reduces the integrated area of a circuit while avoiding an element destruction caused by thermal runaway, and a method of manufacturing the transistor integrated circuit device. A cut capacitor (13) is composed of an upper electrode formed from a wiring metal and in a first layer; and a lower electrode formed from a wiring metal and in a second layer. A bias resistor (12) is formed from the same wiring metal as that of the lower electrode of the cut capacitor (13). This bias resistor (12) is formed from a wiring metal which is made into a thin film to function as a sheet resistor, and the resistance value of the bias resistor (12) can be freely set according to the thickness or width of the wiring metal.
    Type: Application
    Filed: October 8, 2004
    Publication date: June 22, 2006
    Inventors: Katsuhiko Kawashima, Masahiro Maeda, Keiichi Murayama, Hirotaka Miyamoto
  • Publication number: 20060054932
    Abstract: A semiconductor device includes a GaAs substrate, a sub-collector layer provided on the GaAs substrate, a collector layer provided on part of the sub-collector layer, a base layer (first semiconductor layer) provided on the collector layer, a second emitter layer (second semiconductor layer) provided on part of the base layer located in an intrinsic base region, and a first emitter layer provided on the second emitter layer.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 16, 2006
    Inventors: Takahiro Yokoyama, Hirotaka Miyamoto