Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.

Abstract: A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.

Abstract: There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.

Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Abstract: In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.

Abstract: A hybrid circuit includes a resistor inserted serially between a transmission line and an output driver for transmitting a signal; and a reception signal extraction unit for extracting only a reception signal from a signal existing in a transmission path by using a signal obtained from both ends of the resistor. The reception signal extraction unit can be constituted by, for example, two transconductance amplifiers for converting the input voltage into a current and a load resistor in which flows the current of a result of adding the output currents of the two amplifiers.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Abstract: A jitter reduction circuit includes a signal line transmitting a first signal and having a plurality of sections, and a plurality of delay lines transmitting a second signal and provided in one-to-one correspondence to the sections of the signal line, wherein the plurality of delay lines is configured such that a delay of the second signal on a given one of the delay lines is set to a first delay in response to a first level of the first signal in a corresponding one of the sections, and is set to a second delay in response to a second level of the first signal in the corresponding one of the sections.

Abstract: A timing signal generating system has a clock signal generating circuit, a synchronizing circuit, a phase code recognizing circuit, and a calibration circuit. The clock signal generating circuit generates at least one first clock signal upon receipt of at least one reference clock signal by controlling an output phase thereof with a digital code signal. The synchronizing circuit hands over signals between a group of circuits operated by the first clock signal and an internal circuit operated by a second clock signal. The phase code recognizing circuit recognizes a phase code when the phases of the first clock signal and of the second clock signal are in a particular relationship. The calibration circuit calibrates a relationship between a value of the recognized phase code and a phase difference between the first and second clock signals. The synchronizing circuit is controlled by using phase code data calibrated by the calibration circuit.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: This is a data reproduction circuit for receiving data and reproducing the data and its clock which comprises an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.