Patents by Inventor Hirotaka Tamura
Hirotaka Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180018563Abstract: An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated.Type: ApplicationFiled: May 31, 2017Publication date: January 18, 2018Applicant: FUJITSU LIMITEDInventors: Sanroku Tsukamoto, Hirotaka TAMURA, SATOSHI MATSUBARA
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Publication number: 20180005114Abstract: In an information processing apparatus, a calculation circuit calculates energy values representing total energies of Ising devices that are set up with different noise widths, where the Ising devices have equal conditions about neuron-to-neuron connections. An exchange control circuit exchanges output values of neurons or noise widths, between first and second Ising devices having adjacent noise widths. This exchange takes place with an exchange probability based on a difference in the energy values between the first Ising device and the second Ising device.Type: ApplicationFiled: June 1, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: YASUMOTO TOMITA, Hirotaka TAMURA
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Publication number: 20170368682Abstract: A neural network apparatus includes: a plurality of neuron units each including: an adder that performs addition processing and one or more digital analog converters that perform digital-analog conversion processing, relating to weighted inputs; and a delta-sigma analog digital converter that converts an analog signal indicating an added value obtained by adding all of the weighted inputs obtained from the adder and the one or more digital analog converters, into a pulse signal according to an amplitude, and outputs the pulse signal; a plurality of arithmetic units each of which multiplies the pulse signal outputted from one neuron unit by a weighted value, and outputs a result to another neuron unit; and an oscillator that is capable of changing a frequency of a clock signal to be outputted and supplies the clock signal to the neuron unit and the arithmetic unit according to control from a control unit.Type: ApplicationFiled: May 26, 2017Publication date: December 28, 2017Applicant: FUJITSU LIMITEDInventors: Takumi Danjo, Hirotaka TAMURA, Sanroku Tsukamoto
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Publication number: 20170364477Abstract: Arithmetic circuits calculate d?1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.Type: ApplicationFiled: June 7, 2017Publication date: December 21, 2017Applicant: FUJITSU LIMITEDInventors: David Thach, Hirotaka TAMURA, Sanroku Tsukamoto
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Publication number: 20170351947Abstract: Ising devices interconnected via buses each include: neuron circuits that each update, when a value of an output signal from one of connection destination neuron circuits changes, a value based on an update signal; a memory holding connection destination information wherein items of address information respectively identifying the destination neuron circuits and the ising devices including these circuits and identification information about weight values are associated with each other; a control circuit that outputs, when an output signal of a destination neuron circuit in an ising device other than the own ising device changes, the value of the changed output signal and the update signal based on the destination information; and a router that receives a mode set value from a control device and determines whether to connect at least two neighboring ising devices, or a neighboring ising device and the control circuit, based on the set value.Type: ApplicationFiled: May 26, 2017Publication date: December 7, 2017Applicant: FUJITSU LIMITEDInventors: Hirotaka TAMURA, SATOSHI MATSUBARA
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Publication number: 20170351949Abstract: An individual neuron circuit calculates a first value based on a sum of products each obtained by multiplying one of weight values, each representing connection or disconnection between a corresponding neuron circuit and one of the other neuron circuits, by a corresponding one of output signals of the other neuron circuits and outputs 0 or 1, based on a result of comparison between a second value obtained by adding a noise value to the first value and a threshold. An arbitration circuit allows, when first output signals of first neuron circuits interconnected among the neuron circuits simultaneously change based on the weight values, updating of only one of the first output signals of the first neuron circuits and allows, when second output signals of second neuron circuits not interconnected simultaneously change, updating of the second output signals.Type: ApplicationFiled: April 10, 2017Publication date: December 7, 2017Applicant: FUJITSU LIMITEDInventors: SATOSHI MATSUBARA, Hirotaka TAMURA
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Patent number: 9742405Abstract: A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.Type: GrantFiled: July 24, 2014Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventors: Hirotaka Tamura, Hisanori Fujisawa, Hiroaki Fujimoto, Safeen Huda, Jason Anderson
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Publication number: 20170220924Abstract: Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.Type: ApplicationFiled: January 30, 2017Publication date: August 3, 2017Applicant: FUJITSU LIMITEDInventors: Takumi DANJO, Sanroku TSUKAMOTO, Hirotaka TAMURA
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Publication number: 20170004398Abstract: A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.Type: ApplicationFiled: April 15, 2016Publication date: January 5, 2017Applicant: FUJITSU LIMITEDInventors: YANFEI CHEN, Sanroku Tsukamoto, Hirotaka TAMURA
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Patent number: 9213796Abstract: A method for designing a semiconductor integrated circuit includes: determining, by a designing device, first wirings over which signals are propagated and second wirings which are not used for propagation of the signals among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, from among the second wirings, third wirings to be used for storing electrical charges for electrical charge recycling of the first wirings for a most number of the first wirings in a range that satisfies a timing constraint based on operation rates of the signals propagated over the first wirings and delay times of the first wirings.Type: GrantFiled: August 7, 2014Date of Patent: December 15, 2015Assignee: FUJITSU LIMITEDInventors: Hirotaka Tamura, Jason Anderson, Safeen Huda, Hiroaki Fujimoto
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Patent number: 9191187Abstract: A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions.Type: GrantFiled: December 20, 2013Date of Patent: November 17, 2015Assignee: FUJITSU LIMITEDInventors: Takayuki Shibasaki, Hirotaka Tamura
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Patent number: 9160403Abstract: A signal transmission circuit includes a driver circuit that includes complementary inverters, each of the complementary inverters including a plurality of transistor switches, each of the plurality of transistor switches including a pair of transistors, one of the pair of transistors operating in a saturation region and another of the pair of transistors operating in a triode region to cause a certain impedance, and that drives each of the plurality of transistor switches in accordance with complementary signals so as to output complementary voltages to a transmission line; and first voltage sources that supply operating voltages to the driver circuit so as to adjust amplitudes of the complementary voltages output from the driver circuit to the transmission line.Type: GrantFiled: May 6, 2013Date of Patent: October 13, 2015Assignee: FUJITSU LIMITEDInventors: Kosuke Suzuki, Hirotaka Tamura
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Patent number: 9118451Abstract: A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.Type: GrantFiled: February 25, 2014Date of Patent: August 25, 2015Assignee: Fujitsu LimitedInventors: Masaya Kibune, Hirotaka Tamura
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Patent number: 9112673Abstract: A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector.Type: GrantFiled: July 18, 2014Date of Patent: August 18, 2015Assignee: FUJITSU LIMITEDInventors: Shigeto Suzuki, Hirotaka Tamura
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Patent number: 9054714Abstract: A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.Type: GrantFiled: November 5, 2013Date of Patent: June 9, 2015Assignee: FUJITSU LIMITEDInventors: Kosuke Suzuki, Hirotaka Tamura
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Patent number: 9001902Abstract: A transmission system includes: a transmitter configured to transmit a first signal; a receiver configured to receiver a second signal from the transmitter; and a bias circuit configured to regulate a direct current bias level of an input terminal of the receiver, wherein the transmitter includes a first amplitude converter configured to convert the first signal to the second signal having a smaller amplitude than an amplitude of the first signal, wherein the receiver includes a second amplitude converter configured to convert the second signal to a third signal having a larger amplitude than the amplitude of the second signal, and wherein the first amplitude converter includes a first capacitance that restricts an amount of charge to be supplied to the receiver.Type: GrantFiled: January 28, 2013Date of Patent: April 7, 2015Assignee: Fujitsu LimitedInventors: Tadahisa Matsumoto, Hirotaka Tamura
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Patent number: 8989333Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.Type: GrantFiled: September 20, 2013Date of Patent: March 24, 2015Assignee: Fujitsu LimitedInventors: Takushi Hashida, Hirotaka Tamura
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Patent number: 8983013Abstract: A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals.Type: GrantFiled: October 30, 2013Date of Patent: March 17, 2015Assignee: Fujitsu LimitedInventor: Hirotaka Tamura
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Patent number: 8981854Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.Type: GrantFiled: May 2, 2013Date of Patent: March 17, 2015Assignee: Fujitsu LimitedInventors: Yasumoto Tomita, Hirotaka Tamura
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Publication number: 20150061410Abstract: A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.Type: ApplicationFiled: July 24, 2014Publication date: March 5, 2015Inventors: Hirotaka TAMURA, Hisanori FUJISAWA, Hiroaki FUJIMOTO, Safeen HUDA, Jason ANDERSON