Patents by Inventor Hirotsugu Hata

Hirotsugu Hata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190143962
    Abstract: A control system for a vehicle that prevents an unintentional mode change when a command signal cannot be transmitted to an engagement device. In the vehicle, HV-Lo mode is established by connecting a carrier to a carrier by a first clutch while disconnecting the carrier from a ring gear by a second clutch, and HV-Lo mode is established by disconnecting the carrier from the carrier by the first clutch while connecting the carrier to the ring gear by the second clutch. A normally stay clutch is used as at least one of the first clutch and the second clutch.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 16, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tatsuya IMAMURA, Hideaki KOMADA, Akiko NISHIMINE, Yosuke SUZUKI, Hidekazu NAGAI, Takahito ENDO, Hirotsugu YOSHINO, Kensei HATA, Hiroki YASUI
  • Patent number: 8377808
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 19, 2013
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Publication number: 20110165765
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 7, 2011
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7932580
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 26, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7910449
    Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: March 22, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Publication number: 20100279482
    Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.
    Type: Application
    Filed: July 14, 2010
    Publication date: November 4, 2010
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7791171
    Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: September 7, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7719081
    Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: May 18, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Patent number: 7560797
    Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: July 14, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Publication number: 20080191315
    Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 14, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Publication number: 20080150083
    Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 26, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
  • Patent number: 7288816
    Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: October 30, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake, Hirotsugu Hata
  • Publication number: 20070158754
    Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers are formed by being expanded from a surface of a first epitaxial layer. By use of this structure, lateral expansion widths of the P type buried diffusion layers are reduced. Thus, the device size of an NPN transistor can be reduced.
    Type: Application
    Filed: December 7, 2006
    Publication date: July 12, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Publication number: 20070145520
    Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Publication number: 20070145530
    Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Publication number: 20070063274
    Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
    Type: Application
    Filed: February 22, 2006
    Publication date: March 22, 2007
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake, Hirotsugu Hata
  • Patent number: 7135380
    Abstract: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: November 14, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoshi Onai, Hirotsugu Hata
  • Publication number: 20050287765
    Abstract: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented.
    Type: Application
    Filed: June 22, 2005
    Publication date: December 29, 2005
    Inventors: Satoshi Onai, Hirotsugu Hata
  • Patent number: 6545337
    Abstract: Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: April 8, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tadayoshi Takada, Osamu Kitamura, Shigeaki Okawa, Hirotsugu Hata, Chikao Fujinuma
  • Patent number: 6528379
    Abstract: A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: March 4, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tadayoshi Takada, Osamu Kitamura, Shigeaki Okawa, Hirotsugu Hata, Chikao Fujinuma