Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers are formed by being expanded from a surface of a first epitaxial layer. By use of this structure, lateral expansion widths of the P type buried diffusion layers are reduced. Thus, the device size of an NPN transistor can be reduced.

Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented.

Abstract: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented.

Abstract: Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

Abstract: A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.

Abstract: A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.