Abstract: Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

Abstract: A lead electrode is formed to expose an active base region. A lead electrode for an emitter electrode is formed on the lead electrode in an emitter region, through an insulating film. The insulating film on the lead electrode is then etched to form a contact hole. After that, the emitter contact hole is formed to expose the lead electrode. Also, a silicon nitride film SN is interposed between the lead electrode and insulating film and between the lead electrode and LOCOS oxide film each to decrease resistance of the lead electrodes.

Abstract: A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer.

Abstract: A lead electrode (57) is formed to expose an active base region (61). On the lead electrode (57) is formed a lead electrode (64) for an emitter electrode via an insulation film (56). When a base contact hole (65') for exposing the lead electrode (57) and an emitter contact hole for exposing the lead electrode (64) are formed at the same time, total thickness of the insulation film on the lead electrode (64) is thinner than that of the insulation layer on the lead electrode (57), which results in excessive etching on a part of the surface of the lead electrode to form recess. The lead electrode (64) is led out to a LOCOS film to form the emitter contact hole in a region on the LOCOS film to expose the lead electrode (64). Therefore, the recess having been formed on the lead electrode (64) upon forming the emitter contact hole is made to form on the LOCOS film outside the emitter region. The recess prevents depth of the emitter region from dispersing.