Patents by Inventor Hiroyasu Ishizuka
Hiroyasu Ishizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180197850Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.Type: ApplicationFiled: March 12, 2018Publication date: July 12, 2018Inventors: Takeo TOBA, Kazuo TANAKA, Hiroyasu ISHIZUKA
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Patent number: 9947651Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.Type: GrantFiled: June 5, 2013Date of Patent: April 17, 2018Assignee: Renesas Electronics CorporationInventors: Takeo Toba, Kazuo Tanaka, Hiroyasu Ishizuka
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Patent number: 9379100Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: November 28, 2015Date of Patent: June 28, 2016Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20160079231Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: ApplicationFiled: November 28, 2015Publication date: March 17, 2016Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Patent number: 9209811Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: August 15, 2014Date of Patent: December 8, 2015Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20140354331Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: ApplicationFiled: August 15, 2014Publication date: December 4, 2014Inventors: Kazuo SAKAMOTO, Naozumi MORINO, Kazuo TANAKA, Hiroyasu ISHIZUKA
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Patent number: 8810278Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.Type: GrantFiled: October 18, 2012Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20130264647Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: Takeo TOBA, Kazuo TANAKA, Hiroyasu ISHIZUKA
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Patent number: 7924539Abstract: A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.Type: GrantFiled: July 10, 2009Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyasu Ishizuka, Kazuo Tanaka
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Publication number: 20100155845Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.Type: ApplicationFiled: December 18, 2009Publication date: June 24, 2010Inventors: Takeo Toba, Kazuo Tanaka, Hiroyasu Ishizuka
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Publication number: 20090273870Abstract: The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.Type: ApplicationFiled: July 10, 2009Publication date: November 5, 2009Inventors: Hiroyasu Ishizuka, Kazuo Tanaka
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Patent number: 7593201Abstract: A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.Type: GrantFiled: October 20, 2005Date of Patent: September 22, 2009Assignee: Renesas Technology Corp.Inventors: Hiroyasu Ishizuka, Kazuo Tanaka
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Patent number: 7484816Abstract: A vehicle control apparatus for controlling a prime mover and wheel brakes which are equipped in a vehicle with an automatic transmission. The vehicle control apparatus includes a prime mover stopping unit which stops and restarts the prime mover under predetermined conditions, and a braking force retaining unit which retains braking force of each of the wheel brakes. Even if the automatic transmission is set in a neutral range, the braking force retaining unit is controlled to retain the braking force of the wheel brakes for a first predetermined time after the operation of a brake operation member is disengaged.Type: GrantFiled: November 23, 2005Date of Patent: February 3, 2009Assignee: Honda Motor Co., Ltd.Inventors: Takahumi Maruyama, Toshitaka Imai, Seiji Ohsaki, Hiroyasu Ishizuka
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Publication number: 20070114841Abstract: A vehicle control apparatus for controlling a prime mover and wheel brakes which are equipped in a vehicle with an automatic transmission. The vehicle control apparatus includes a prime mover stopping unit which stops and restarts the prime mover under predetermined conditions, and a braking force retaining unit which retains braking force of each of the wheel brakes. Even if the automatic transmission is set in a neutral range, the braking force retaining unit is controlled to retain the braking force of the wheel brakes for a first predetermined time after the operation of a brake operation member is disengaged.Type: ApplicationFiled: November 23, 2005Publication date: May 24, 2007Applicant: Honda Motor Co., Ltd.Inventors: Takahumi Maruyama, Toshitaka Imai, Seiji Ohsaki, Hiroyasu Ishizuka
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Patent number: 7125085Abstract: A braking force retaining unit has a cut-off valve and a control unit. The cut-off valve retains predetermined brake hydraulic pressure at the wheel cylinders until a predetermined releasing condition is established, even after the depression of a brake pedal is released when a vehicle is stopped. When the predetermined releasing condition is established, the retained brake hydraulic pressure is released, when the depression of the brake pedal is released, the control unit controls the cut-off valve so as to retain the brake hydraulic pressure while reducing the retained brake hydraulic pressure at a first reduction rate. When the predetermined releasing condition is established, the control unit controls the cut-off valve so as to allow the retained brake hydraulic pressure to be reduced at a second reduction rate which is faster than the first reduction rate.Type: GrantFiled: September 21, 2005Date of Patent: October 24, 2006Assignee: Honda Motor Co., Ltd.Inventors: Seiji Ohsaki, Hiroyasu Ishizuka
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Publication number: 20060108868Abstract: A braking force retaining unit has a cut-off valve and a control unit. The cut-off valve retains predetermined brake hydraulic pressure at the wheel cylinders until a predetermined releasing condition is established even after the depression of a brake pedal is released when a vehicle is stopped, whereas when the predetermined releasing condition is established, the brake hydraulic pressure so retained is released, when the depression of the brake pedal is released, the control unit controls the cut-off valve so as to retain the brake hydraulic pressure while reducing the retained brake hydraulic pressure at a first reduction speed. When the predetermined releasing condition is established, the control unit controls the cut-off valve so as to allow the brake hydraulic pressure retained at the wheel cylinders to be reduced at a second reduction speed which is faster than the first reduction speed.Type: ApplicationFiled: September 21, 2005Publication date: May 25, 2006Applicant: Honda Motor Co., Ltd.Inventors: Seiji Ohsaki, Hiroyasu Ishizuka
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Publication number: 20060087781Abstract: The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.Type: ApplicationFiled: October 20, 2005Publication date: April 27, 2006Inventors: Hiroyasu Ishizuka, Kazuo Tanaka
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Publication number: 20060077601Abstract: The invention intends to provide a semiconductor device capable of preventing an electrostatic breakdown especially by the CDM, of the electrostatic breakdowns generated between plural power supply systems, with a few number of protection circuits. The semiconductor device includes a first circuit block that operates with a first power supply voltage and a first reference voltage, and a second circuit block that operates with a second power supply voltage and a second reference voltage. Further, the semiconductor device includes a first clamp circuit that clamps a potential between the first power supply voltage and the second reference voltage, a second clamp circuit that clamps a potential between the second power supply voltage and the first reference voltage, and a third clamp circuit that clamps a potential between the first reference voltage and the second reference voltage.Type: ApplicationFiled: September 12, 2005Publication date: April 13, 2006Inventors: Hiroyuki Ikeda, Kazuo Tanaka, Hiroyasu Ishizuka, Koichiro Takakuwa
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Publication number: 20060061211Abstract: A braking force retaining unit includes a cut-off valve disposed between a master cylinder and wheel cylinders in a brake hydraulic circuit. The cut-off valve being adopted to retain predetermined brake hydraulic pressure until a predetermined releasing condition is established even after the depression of a brake pedal is released when a vehicle is stopped, a one-way valve provided in parallel with the cut-off valve and adapted to permit a one-way passage of a brake fluid from a master cylinder side to a wheel cylinder side, a further application detecting sensor for detecting a further application of brakes, a further application determination unit for determining on an existence of the further application of brakes based an input from the further application detecting sensor and a valve control unit for opening the cut-off valve when the further application determination unit determines that the further application of brakes is occurred.Type: ApplicationFiled: September 21, 2005Publication date: March 23, 2006Applicant: Honda Motor Co., Ltd.Inventors: Seiji Ohsaki, Hiroyasu Ishizuka
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Patent number: 6828842Abstract: A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.Type: GrantFiled: May 22, 2003Date of Patent: December 7, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co, Ltd.Inventors: Kayoko Saito, Mitsugu Kusunoki, Hiroyasu Ishizuka, Shinichiro Masuda