Abstract: A voltage detecting circuit includes a constant-voltage source, a load part including a first transistor coupled to the constant-voltage source, and a detecting part which is connected to the load part and includes a second transistor of the same type as that of the first transistor. The detecting part detects a given voltage applied thereto.

Abstract: A semiconductor device comprising a dummy interface circuit approximating to an external interface circuit with high accuracy is disclosed. The device further comprises a dummy interface circuit for internally generating, by simulation, a dummy output signal equivalent to the level of the output signal of the external interface circuit. The dummy interface circuit includes a dummy signal output circuit for producing a dummy output signal at a dummy output line, a dummy capacitor connected to the dummy output line, and a dummy load circuit connected to the dummy output line for converting the dummy output signal into a signal of a level corresponding to the output signal level of the external interface.

Abstract: A semiconductor device includes a first terminal for inputting and outputting data and a second terminal for inputting control data in synchronization with a strobe signal. The semiconductor device includes an equivalent circuit which is provided in the second terminal. Further, the equivalent circuit has a capacitance which is equivalent to that in an output circuit which is provided in the first terminal.

Abstract: In performing a read operation or a write operation in a memory cell, a row control circuit is first operated to activate a word line. Subsequently, a command control circuit receives a column operation command in synchronization with a clock signal so as to operate a column control circuit. Here, under the control of a timing adjusting circuit, the column control circuit starts operating a predetermined delay time after the reception of the column operation command. By delaying the operation of the column control circuit, the read operation or the write operation in the memory cell can be performed at the optimum timing corresponding to the operating timing of an internal circuit independent of the cycle of the clock signal. As a result, the number of times in receiving commands per unit time can be increased to enhance the bus occupation rate of data.

Abstract: When a plurality of commands are received in succession to read/write data from/to memory cells in accordance with the combination of these commands, a word line for controlling the transfer switches of the memory cells are activated after the reception of one of the commands excluding the first command. This allows control circuits for activating the word lines to be operated at a lower frequency than heretofore, with a reduction in power consumption. Moreover, the word lines are activated based on an address signal that is supplied along with the first command as well as a part of an address signal supplied along with one of the commands excluding the first command. Consequently, the memory region to be selected by these address signals can be smaller, with a reduction in power consumption.

Abstract: A delay circuit including a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators generates a clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. The subsequent interpolators operate as delay stages, thereby generating a delayed clock signal delaying from the reference clock signal by a predetermined time. It is possible to make smaller the minimum unit of a delay adjustment to the delayed clock signal by using the interpolators.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

Abstract: The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A semiconductor integrated circuit comprising: a pair of memory cores in which identical data are written; a refresh signal generating circuit; a refresh controlling circuit; and a read controlling circuit. The memory cores are operated during each predetermined period as refresh cores for performing a refresh operation and as read cores for performing a read operation. The refresh core performs refresh and write operations. The read core performs read and write operations. The write cycle time defined as an operation specification is set longer than the time necessary for each of the memory cores to perform a write operation. Therefore, during the refresh core, the time difference between the write cycle and the write operation is summed up during a plurality of write cycles to create a predetermined time margin.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.

Abstract: A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area.

Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

Abstract: A command receiving circuit receives a command signal for determining a circuit operation, in synchronization with a clock signal and it outputs the received command signal as an internal command signal. An address switching circuit permits transmission of an address signal to an internal circuit upon receiving the command signal. The internal circuit receives the address signal before the reception of the command signal, thereby to start its operation. As a result, the internal circuit can be operated at high speed. Besides, the address switching circuit inhibits the transmission of the address signal to the internal circuit upon receiving the internal command signal or the clock signal. Therefore, even when the level of the address signal has changed after the reception of the command signal, the change does not lead to operating the internal circuit. Accordingly, the power consumption of the semiconductor integrated circuit is reduced.

Abstract: A variable delay circuit includes a load on a signal transfer line, at least one transistor connected in parallel with the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

Abstract: A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.