Abstract: A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A semiconductor integrated circuit includes an internal clock generating circuit generating an internal clock, and a flip-flop circuit configured so that n latch circuits are cascaded via switch circuits performing switching operations in synchronism with the internal clock where n is an integer equal to or greater than 2. An initialization control circuit is provided so that it applies, after power on, an initialization signal to the flip-flop circuit whereby a first latch circuit among the n latch circuits is initialized. The initialization control circuit causes the internal clock generating circuit to generate the internal clock during a predetermined period so that the second through nth latch circuits are sequentially initialized.

Abstract: A semiconductor device outputs data from a plurality of data nodes during a normal-operation mode, and outputs a test result from at least one of the data nodes during a test-operation mode. The semiconductor device includes a plurality of data-bus lines which convey the data with respect to the data nodes, and a data-bus switch which allows only the data-bus lines corresponding to the at least one of the data nodes to be driven in a first condition of the test-operation mode, and which allows all of the data-bus lines corresponding to the data nodes to be driven in a second condition of the test-operation mode.

Abstract: A semiconductor device for accepting a data from outside in synchronization with data strobe signal. The semiconductor device includes control circuit for generating an accept-control signal which is activated in response to a write command inputted in synchronization with a clock signal and is inactivated in response to the data strobe signal in synchronization with the final data signal, and data input circuit for accepting the data signals while the accept-control signal is activated. The timing of the accept-control signal varies in accordance with the variation of the timing of the data strobe signal because the control circuit controls so as to inactivate the accept-control signal in response to the data strobe signal. Hence, inactivating of the accept-control signal is always performed within a predetermined time period after the final data signal is accepted in synchronization with the data strobe signal.

Abstract: A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.

Abstract: A semiconductor device includes a variable-delay circuit which delays an input-clock signal to generate a delay clock signal, a clock-control circuit which selects one of the input-clock signal and the delayed clock signal, an output circuit which outputs data in synchronism with a clock signal selected by the clock-control circuit, and a DLL circuit which adjusts a delay of the variable-delay circuit. The DLL circuit includes a delay-control circuit which adjusts the delay of the variable-delay circuit, and a clock-selection circuit which controls the clock-control circuit to select one of the input-clock signal and the delayed clock signal. The variable-delay circuit is controlled such that the delay is not increased when the input-clock signal is selected by the clock-selection circuit.

Abstract: The present invention internally latches a write data signal applied in synchronous with an external data strobe signal in response to an internal data strobe signal which is generated in response to this external data strobe signal, and furthermore, supplies the write data signal to a memory cell array from a write circuit such as a write amplifier in response to a write signal generated from this external data strobe signal. Meanwhile, an address signal is introduced internally in accordance with an external clock. Therefore, since the driving of the data bus connected to a memory cell array from a write amplifier, which constitutes a write operation internal to memory, commences in accordance with an external data strobe signal, a write operation can be ended in the shortest possible time from write data signal input. The above-described invention is especially effective when memory comprises a 2-bit pre-fetch.

Abstract: A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Abstract: A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree.

Abstract: A semiconductor memory device, to which a plurality of command signals are supplied in synchronous with a clock, comprises a plurality of input circuits, having a sampling unit for inputting said command signals and said clock and sampling said command signals in synchronous with said clock, and an output unit for outputting said sampled command signals; a command decoder for receiving the command signals output by said plurality of input circuits, decoding said plurality of command signals and generating a corresponding control signal; a memory element, which implements a variety of operational modes in response to said control signals; an output timing signal generator circuit, having a circuit architecture equivalent to at least the sampling unit of said input circuit, for sampling a predetermined signal level in synchronous with said clock, and for generating an output timing signal based on the timing of the operational delay time of said sampling unit; and wherein said input circuit outputs said sampled

Abstract: In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

Abstract: A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs.

Abstract: In the present invention data from the odd memory cell array is latched to a data-hold circuit at a fast timing, which ignores the delay time of the +1 arithmetic circuit, and outputs that data to the output terminal. Further, when the supplied column address is even, data from the even memory cell array is latched to a data-hold circuit at a fast timing similar to that described above, and when the column address is odd, this data is latched to a data-hold circuit with a delay equivalent to the delay of the +1 arithmetic circuit. In this case, since the output of even output data to an output terminal occurs following the output of odd output data, the overall output operation is not affected comparing to the conventional one. Another aspect of the present invention provides a circuit, which shifts one bit combinations of the second and third bits following the least significant bit in a column address.

Abstract: A semiconductor memory device includes a plurality of memory cells coupled to word lines having a first end and a second end opposite to the first end, a word line driving circuit, and a word line resetting circuit. The word line driving circuit has at least one p-channel field effect transistor which is located in a vicinity of the first end of the word lines and drives a corresponding one of the word lines. On the other hand, the word line resetting circuit has at least one n-channel field effect transistor which is located in a vicinity of the second end of the word lines and resets a corresponding one of the word lines.

Abstract: A semiconductor apparatus includes a voltage unit which supplies a down voltage produced at a node, the voltage unit having a plurality of resistors connected in series between a power supply line and a grounding line, the node being a connection point between the plurality of resistors. A backup unit pulls up the node of the voltage unit when a voltage at the node is below a lower limit of the down voltage, so that the voltage at the node increases to the lower limit, and pulls down the node of the voltage unit when the voltage at the node is above an upper limit of the down voltage, so that the voltage at the node decreases to the upper limit. A control unit sets the backup unit in one of an active state and an inactive state in response to a control signal.