Abstract: A silicon carbide layer has an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction. First well regions are arranged in the active region. A second well region is arranged in the outer peripheral region. Ohmic electrodes are arranged on a second surface of the silicon carbide layer, are connected to a source electrode, are electrically and ohmically connected to the first well regions, and have surface regions ohmically contacting a part forming the second surface of the silicon carbide layer and having a second conductivity type. The active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region. The surface regions are arranged at surface density lower in the thinned region part than in the standard region part in a plan view.

Abstract: Fluctuations in device characteristics are suppressed by suppressing local occurrences of a large current through a body diode of a field-effect transistor. A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate, and a backside electrode formed on the lower surface of the silicon carbide semiconductor substrate. A region in which electric resistivity takes a first value is regarded as a first resistance region, and a region where the electric resistivity takes a second value greater than the first value is regarded as a second resistance region. The second resistance region extends across a region boundary, i.e., the boundary between the active region and the termination region, in plan view.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.

Abstract: External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel width W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2·Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1·Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1).

Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.

Abstract: External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel width W2 each (in steps 100 and 104).

Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.

Abstract: MOS transistors (TR1, TR2) are arranged closer to a pad (SP) in descending order of current-driving capability. Namely, the MOS transistors (TR1, TR2) are arranged from closer part to the pad (SP) in descending order of value of W/L obtained by dividing a gate width (W) of a gate electrode by a gate length (L) of the same. When a transistor has a large current-driving capability, the value of source-to-drain current is high. For this reason, the MOS transistors are arranged from closer part to the pad for source electrode in descending order of current-driving capability, to thereby reduce the amount of voltage drop in an interconnect line. A current value of the transistor becomes lower as a distance between the pad and the transistor increases. As a result, it is allowed to reduce influence on the transistor characteristics exerted by voltage drop due to interconnection resistance.

Abstract: External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel with W2 each (in steps 100 and 104).

Abstract: A method of fabricating a semiconductor device includes burying Cu wiring with an insulating interlayer film and a first insulating film for preventing diffusion of copper on a planarized surface, including the Cu wiring, of which copper is the uppermost layer, and with a second insulating film having high moisture resistance. A photosensitive polyimide material is applied to the insulating film, exposed, and developed, thereby forming an etching mask. The etching mask is cured. Using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulating films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A semiconductor device evaluation method and apparatus are provided which do not require a measurer to expend a great deal of time and effort even when measuring a large number of points, can prevent the occurrence of variations in measured values from measurer to measurer, and allow the measurement of the finished gate length even if gate pattern does not appear on the semiconductor device surface. There is also provided a semiconductor device manufacturing control method which applies such an evaluation method and apparatus to the control of semiconductor device manufacturing. For a plurality of insulated gate transistors with different channel lengths, an effective channel length (Leff), a gate capacitance (Cg), and a fringing capacitance (Cf) are determined by electrical measurement and/or calculation. The gate capacitance (Cg) and the effective channel length (Leff) are extended on a graph by extrapolation to determine gate-capacitance-vs.-effective-channel-length characteristics.