Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

Abstract: To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10).

Abstract: A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10).

Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.

Abstract: A metal wire comprising a metal member and a barrier metal is formed within each of trenches formed in an insulating film placed on a semiconductor substrate. A first metal diffusion preventive film is formed on the insulating film so as to make contact with an upper portion of the barrier metal formed on the sides of the metal. Further, a second metal diffusion preventive film is formed on the first metal diffusion preventive film and the metal wire.

Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.

Abstract: A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first polysilicon film is formed on the first polysilicon film. The second polysilicon film is anisotropically etched to expose a surface of the first polysilicon film. Thermal oxidation is then performed. A surface of the first polysilicon film and a surface of the second polysilicon film are oxidized according to their respective oxidization rates depending on their respective phosphorus concentrations. Thus, a semiconductor device in which the size of the gate electrode can be readily controlled and damage to the semiconductor substrate or the like can be suppressed, is obtained.

Abstract: An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

Abstract: A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic cell arranging and wiring process part for generating layout designing data by utilizing a structure description part which is a control description for defining the arrangement method and the wiring method of the basic cells, the designation parameter, the structure description, and the basic cells. Furthermore, it includes a basic cell generating process part for generating the newly designated basic cells in accordance with the designation parameter.

Abstract: The semiconductor memory device includes a memory cell array for storing a plurality of data on a word basis, a data input-output device and a read control device. The data input-output device includes a plurality of data holding circuits corresponding to one word. The data of one word is divided into a plurality of subwords. The read control device brings to an active state any one of a plurality of control signals corresponding to the plurality of subwords in response to an externally applied subword selection signal. The data holding circuit corresponding to one subword is thereby activated. As a result, any subword among the data of one word held in the data holding circuit is rewritten with a corresponding subword among the data of one word read from the memory cell array.