Patents by Inventor Hiroyuki Chibahara

Hiroyuki Chibahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967471
    Abstract: The present disclosure aims to provide an electrical contact to which a low boiling point metal is added, the electrical contact being able secure both mechanical strength and conductivity at the same time. The electrical contact according to the present disclosure includes a base material made of Cu, particles of a high melting point substance dispersed in the base material, the particles being made of at least one of a high melting point metal or a carbide of the high melting point metal, and Te and Ti dispersed in the base material, wherein, the Te of 3.5 to 14.5 mass % is added where the total is 100 mass %, and Ti/Te is 0.12 to 0.38.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 23, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasutomo Tanihara, Hiroyuki Chibahara, Taiki Donen, Satoshi Ochi, Yuichi Takai
  • Publication number: 20220389546
    Abstract: A Super Invar alloy includes Ni of 30 to 35 percent by mass, Co of 3 to 6 percent by mass, Ti of 0.02 to 1.0 percent by mass, Mn of 0 to 0.2 percent by mass, an inevitable impurity including S, and the balance Fe. The Super Invar alloy does not include an additive other than Ti and Mn, as an additive. The Super Invar alloy includes the Ni of 32.3 to 32.5 percent by mass, the Co of 4.4 to 5.1 percent by mass, the Ti of 0.02 to 1.0 percent by mass, and the S of 0.007 to 0.1 percent by mass. The Super Invar alloy is an alloy having good high temperature ductility, low hot crack sensitivity, and low thermal expansibility of equal to or lower than 1 ppm/° C. It is applicable to use Zr or Hf instead of Ti.
    Type: Application
    Filed: December 13, 2019
    Publication date: December 8, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA
  • Patent number: 11462367
    Abstract: Provided is a method of manufacturing a contact material, including the steps of: forming a Ni alloy film having a film thickness of 40 nm or more and 110 nm or less on a surface of WC powder having an average particle diameter of 2 ?m or more and 10 ?m or less by an electroless Ni plating method; performing heat treatment for degassing at a temperature of 500° C. or more and 860° C. or less; crushing Ni alloy-coated WC powder after the heat treatment; mixing the crushed Ni alloy-coated WC powder and Cu powder having an average particle diameter of 1 ?m or more and 100 ?m or less; and compressing the resultant mixture, followed by sintering the mixture at a temperature of more than 1,083° C. and less than 1,455° C.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 4, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hiroyuki Chibahara
  • Publication number: 20220254577
    Abstract: The present disclosure aims to provide an electrical contact to which a low boiling point metal is added, the electrical contact being able secure both mechanical strength and conductivity at the same time. The electrical contact according to the present disclosure includes a base material made of Cu, particles of a high melting point substance dispersed in the base material, the particles being made of at least one of a high melting point metal or a carbide of the high melting point metal, and Te and Ti dispersed in the base material, wherein, the Te of 3.5 to 14.5 mass % is added where the total is 100 mass %, and Ti/Te is 0.12 to 0.38.
    Type: Application
    Filed: August 27, 2019
    Publication date: August 11, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA, Taiki DONEN, Satoshi OCHI, Yuichi TAKAI
  • Patent number: 11066731
    Abstract: In an electric contact including a base material, high-melting-point substance particles, and an intermetallic compound, the intermetallic compound containing a MnX compound (X represents Te or Se) and a compound of a Mn—Cu solid-solution phase and X, is dispersed in the base material. If the Vickers hardness of the high-melting-point substance particles is higher than 0 Hv and lower than 200 Hv, the particle diameter of the high-melting-point substance particles is not smaller than 0.1 ?m and not larger than 100 ?m. If the Vickers hardness of the high-melting-point substance particles is 200 Hv or higher, the particle diameter is not smaller than 0.1 ?m and not larger than 10 ?m. The mass of X atoms is not lower than 1.5 mass % and not higher than 15 mass %. The atomic weight ratio Mn/(Mn+X) is not lower than 20 at % and not higher than 80 at %.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 20, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasutomo Tanihara, Hiroyuki Chibahara, Taiki Donen, Satoshi Ochi, Takayuki Itotani
  • Publication number: 20200277688
    Abstract: In an electric contact including a base material, high-melting-point substance particles, and an intermetallic compound, the intermetallic compound containing a MnX compound (X represents Te or Se) and a compound of a Mn—Cu solid-solution phase and X, is dispersed in the base material. If the Vickers hardness of the high-melting-point substance particles is higher than 0 Hv and lower than 200 Hv, the particle diameter of the high-melting-point substance particles is not smaller than 0.1 ?m and not larger than 100 ?m. If the Vickers hardness of the high-melting-point substance particles is 200 Hv or higher, the particle diameter is not smaller than 0.1 ?m and not larger than 10 ?m. The mass of X atoms is not lower than 1.5 mass % and not higher than 15 mass %. The atomic weight ratio Mn/(Mn+X) is not lower than 20 at % and not higher than 80 at %.
    Type: Application
    Filed: July 13, 2018
    Publication date: September 3, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA, Taiki DONEN, Satoshi OCHI, Takayuki ITOTANI,
  • Patent number: 10629397
    Abstract: A contact member according to the present invention includes: a contact layer composed of a plate-shaped porous body containing a high-melting-point metal as a main constituent and infiltrated with an infiltrant containing a low-melting-point metal as a main constituent; a contact-layer supporting part composed of the infiltrant; and a contact-part holding conductor composed of the infiltrant, wherein, the porous body is provided with an opening at the center of the contact layer and a portion from the opening to the contact-part holding conductor is continuously and integrally molded with the infiltrant.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Chibahara
  • Publication number: 20190378664
    Abstract: Provided is a method of manufacturing a contact material, including the steps of: forming a Ni alloy film having a film thickness of 40 nm or more and 110 nm or less on a surface of WC powder having an average particle diameter of 2 ?m or more and 10 ?m or less by an electroless Ni plating method; performing heat treatment for degassing at a temperature of 500° C. or more and 860° C. or less; crushing Ni alloy-coated WC powder after the heat treatment; mixing the crushed Ni alloy-coated WC powder and Cu powder having an average particle diameter of 1 ?m or more and 100 ?m or less; and compressing the resultant mixture, followed by sintering the mixture at a temperature of more than 1,083° C. and less than 1,455° C.
    Type: Application
    Filed: October 24, 2017
    Publication date: December 12, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hiroyuki CHIBAHARA
  • Publication number: 20190051475
    Abstract: A contact member according to the present invention includes: a contact layer composed of a plate-shaped porous body containing a high-melting-point metal as a main constituent and infiltrated with an infiltrant containing a low-melting-point metal as a main constituent; a contact-layer supporting part composed of the infiltrant; and a contact-part holding conductor composed of the infiltrant, wherein, the porous body is provided with an opening at the center of the contact layer and a portion from the opening to the contact-part holding conductor is continuously and integrally molded with the infiltrant.
    Type: Application
    Filed: January 20, 2017
    Publication date: February 14, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventor: Hiroyuki CHIBAHARA
  • Patent number: 8829679
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20120267793
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Patent number: 8232650
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20110266657
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Patent number: 7998839
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20110121419
    Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
  • Patent number: 7906346
    Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: March 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shuichi Ueno, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
  • Publication number: 20100261334
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 14, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Hiroyuki CHIBAHARA, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Patent number: 7759798
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20090294912
    Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
    Type: Application
    Filed: April 20, 2009
    Publication date: December 3, 2009
    Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
  • Publication number: 20090039451
    Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 12, 2009
    Inventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita