Patents by Inventor Hiroyuki Chibahara
Hiroyuki Chibahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967471Abstract: The present disclosure aims to provide an electrical contact to which a low boiling point metal is added, the electrical contact being able secure both mechanical strength and conductivity at the same time. The electrical contact according to the present disclosure includes a base material made of Cu, particles of a high melting point substance dispersed in the base material, the particles being made of at least one of a high melting point metal or a carbide of the high melting point metal, and Te and Ti dispersed in the base material, wherein, the Te of 3.5 to 14.5 mass % is added where the total is 100 mass %, and Ti/Te is 0.12 to 0.38.Type: GrantFiled: August 27, 2019Date of Patent: April 23, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasutomo Tanihara, Hiroyuki Chibahara, Taiki Donen, Satoshi Ochi, Yuichi Takai
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Publication number: 20220389546Abstract: A Super Invar alloy includes Ni of 30 to 35 percent by mass, Co of 3 to 6 percent by mass, Ti of 0.02 to 1.0 percent by mass, Mn of 0 to 0.2 percent by mass, an inevitable impurity including S, and the balance Fe. The Super Invar alloy does not include an additive other than Ti and Mn, as an additive. The Super Invar alloy includes the Ni of 32.3 to 32.5 percent by mass, the Co of 4.4 to 5.1 percent by mass, the Ti of 0.02 to 1.0 percent by mass, and the S of 0.007 to 0.1 percent by mass. The Super Invar alloy is an alloy having good high temperature ductility, low hot crack sensitivity, and low thermal expansibility of equal to or lower than 1 ppm/° C. It is applicable to use Zr or Hf instead of Ti.Type: ApplicationFiled: December 13, 2019Publication date: December 8, 2022Applicant: Mitsubishi Electric CorporationInventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA
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Patent number: 11462367Abstract: Provided is a method of manufacturing a contact material, including the steps of: forming a Ni alloy film having a film thickness of 40 nm or more and 110 nm or less on a surface of WC powder having an average particle diameter of 2 ?m or more and 10 ?m or less by an electroless Ni plating method; performing heat treatment for degassing at a temperature of 500° C. or more and 860° C. or less; crushing Ni alloy-coated WC powder after the heat treatment; mixing the crushed Ni alloy-coated WC powder and Cu powder having an average particle diameter of 1 ?m or more and 100 ?m or less; and compressing the resultant mixture, followed by sintering the mixture at a temperature of more than 1,083° C. and less than 1,455° C.Type: GrantFiled: October 24, 2017Date of Patent: October 4, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Hiroyuki Chibahara
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Publication number: 20220254577Abstract: The present disclosure aims to provide an electrical contact to which a low boiling point metal is added, the electrical contact being able secure both mechanical strength and conductivity at the same time. The electrical contact according to the present disclosure includes a base material made of Cu, particles of a high melting point substance dispersed in the base material, the particles being made of at least one of a high melting point metal or a carbide of the high melting point metal, and Te and Ti dispersed in the base material, wherein, the Te of 3.5 to 14.5 mass % is added where the total is 100 mass %, and Ti/Te is 0.12 to 0.38.Type: ApplicationFiled: August 27, 2019Publication date: August 11, 2022Applicant: Mitsubishi Electric CorporationInventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA, Taiki DONEN, Satoshi OCHI, Yuichi TAKAI
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Patent number: 11066731Abstract: In an electric contact including a base material, high-melting-point substance particles, and an intermetallic compound, the intermetallic compound containing a MnX compound (X represents Te or Se) and a compound of a Mn—Cu solid-solution phase and X, is dispersed in the base material. If the Vickers hardness of the high-melting-point substance particles is higher than 0 Hv and lower than 200 Hv, the particle diameter of the high-melting-point substance particles is not smaller than 0.1 ?m and not larger than 100 ?m. If the Vickers hardness of the high-melting-point substance particles is 200 Hv or higher, the particle diameter is not smaller than 0.1 ?m and not larger than 10 ?m. The mass of X atoms is not lower than 1.5 mass % and not higher than 15 mass %. The atomic weight ratio Mn/(Mn+X) is not lower than 20 at % and not higher than 80 at %.Type: GrantFiled: July 13, 2018Date of Patent: July 20, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasutomo Tanihara, Hiroyuki Chibahara, Taiki Donen, Satoshi Ochi, Takayuki Itotani
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Publication number: 20200277688Abstract: In an electric contact including a base material, high-melting-point substance particles, and an intermetallic compound, the intermetallic compound containing a MnX compound (X represents Te or Se) and a compound of a Mn—Cu solid-solution phase and X, is dispersed in the base material. If the Vickers hardness of the high-melting-point substance particles is higher than 0 Hv and lower than 200 Hv, the particle diameter of the high-melting-point substance particles is not smaller than 0.1 ?m and not larger than 100 ?m. If the Vickers hardness of the high-melting-point substance particles is 200 Hv or higher, the particle diameter is not smaller than 0.1 ?m and not larger than 10 ?m. The mass of X atoms is not lower than 1.5 mass % and not higher than 15 mass %. The atomic weight ratio Mn/(Mn+X) is not lower than 20 at % and not higher than 80 at %.Type: ApplicationFiled: July 13, 2018Publication date: September 3, 2020Applicant: Mitsubishi Electric CorporationInventors: Yasutomo TANIHARA, Hiroyuki CHIBAHARA, Taiki DONEN, Satoshi OCHI, Takayuki ITOTANI,
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Patent number: 10629397Abstract: A contact member according to the present invention includes: a contact layer composed of a plate-shaped porous body containing a high-melting-point metal as a main constituent and infiltrated with an infiltrant containing a low-melting-point metal as a main constituent; a contact-layer supporting part composed of the infiltrant; and a contact-part holding conductor composed of the infiltrant, wherein, the porous body is provided with an opening at the center of the contact layer and a portion from the opening to the contact-part holding conductor is continuously and integrally molded with the infiltrant.Type: GrantFiled: January 20, 2017Date of Patent: April 21, 2020Assignee: Mitsubishi Electric CorporationInventor: Hiroyuki Chibahara
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Publication number: 20190378664Abstract: Provided is a method of manufacturing a contact material, including the steps of: forming a Ni alloy film having a film thickness of 40 nm or more and 110 nm or less on a surface of WC powder having an average particle diameter of 2 ?m or more and 10 ?m or less by an electroless Ni plating method; performing heat treatment for degassing at a temperature of 500° C. or more and 860° C. or less; crushing Ni alloy-coated WC powder after the heat treatment; mixing the crushed Ni alloy-coated WC powder and Cu powder having an average particle diameter of 1 ?m or more and 100 ?m or less; and compressing the resultant mixture, followed by sintering the mixture at a temperature of more than 1,083° C. and less than 1,455° C.Type: ApplicationFiled: October 24, 2017Publication date: December 12, 2019Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hiroyuki CHIBAHARA
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Publication number: 20190051475Abstract: A contact member according to the present invention includes: a contact layer composed of a plate-shaped porous body containing a high-melting-point metal as a main constituent and infiltrated with an infiltrant containing a low-melting-point metal as a main constituent; a contact-layer supporting part composed of the infiltrant; and a contact-part holding conductor composed of the infiltrant, wherein, the porous body is provided with an opening at the center of the contact layer and a portion from the opening to the contact-part holding conductor is continuously and integrally molded with the infiltrant.Type: ApplicationFiled: January 20, 2017Publication date: February 14, 2019Applicant: Mitsubishi Electric CorporationInventor: Hiroyuki CHIBAHARA
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Patent number: 8829679Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: GrantFiled: June 27, 2012Date of Patent: September 9, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Publication number: 20120267793Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: Renesas Electronics CorporationInventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Patent number: 8232650Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: GrantFiled: July 11, 2011Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Publication number: 20110266657Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: Renesas Electronics CorporationInventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Patent number: 7998839Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: GrantFiled: June 23, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Publication number: 20110121419Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
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Patent number: 7906346Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: GrantFiled: August 7, 2008Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Shuichi Ueno, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
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Publication number: 20100261334Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Applicant: Renesas Technology Corp.Inventors: Hiroyuki CHIBAHARA, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Patent number: 7759798Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: GrantFiled: April 20, 2009Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Publication number: 20090294912Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: ApplicationFiled: April 20, 2009Publication date: December 3, 2009Inventors: Hiroyuki Chibahara, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Publication number: 20090039451Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: ApplicationFiled: August 7, 2008Publication date: February 12, 2009Inventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita