Patents by Inventor Hiroyuki Chibahara

Hiroyuki Chibahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6727170
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: April 27, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
  • Patent number: 6602725
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Patent number: 6383910
    Abstract: There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: May 7, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masakazu Okada, Keiichi Higashitani, Hiroyuki Chibahara
  • Publication number: 20020014682
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Application
    Filed: September 26, 2001
    Publication date: February 7, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Publication number: 20020016059
    Abstract: There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.
    Type: Application
    Filed: March 8, 2001
    Publication date: February 7, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masakazu Okada, Keiichi Higashitani, Hiroyuki Chibahara
  • Publication number: 20010050440
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 13, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
  • Patent number: 6303944
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: October 16, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Patent number: 6278187
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: August 21, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki