Patents by Inventor Hiroyuki Doi

Hiroyuki Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040253102
    Abstract: To provide a rotor material preferable for a steam turbine of which main steam temperature is 675° C. or more, particularly exceeding 700° C., and a steam turbine plant having a rotor formed by the material, the invention provides a steam turbine plant including a very-high-pressure turbine of which steam inlet temperature is 675 to 725° C. and steam outlet temperature is 650° C. or less, a high-pressure turbine, and a medium-low-pressure turbine, wherein a rotor of the very-high-pressure turbine is formed from a forged material of NiFe-base alloy containing: 14 to 18 weight % Cr, 15 to 45 weight % Fe, 1.0 to 2.0 weight % Al, 1.0 to 1.8 weight % Ti, C and N of which the sum is 0.05 or less weight %, and Nb in the range specified by the formula: 3.5−(Fe weight %)/20<(Nb weight %)<4.5−(Fe weight %)/20.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 16, 2004
    Inventors: Shinya Imano, Hiroyuki Doi, Hirotsugu Kawanaka, Eiji Saitou
  • Patent number: 6818077
    Abstract: A nickel-based superalloy containing 12.0 to 16.0% by weight of Cr, 4.0 to 9.0% by weight of Co, 3.4 to 4.6% by weight of Al, 0.5 to 1.6% by weight of Nb, 0.05 to 0.16% by weight of C, 0.005 to 0.025% by weight of B, and at least one of Ti, Ta and Mo. Amounts of Ti, Ta and Mo are ones calculated by the equations (1) and (2), wherein TiEq is 4.0 to 6.0 and MoEq is 5.0 to 8.0. TiEq=Ti % by weight+0.5153×Nb % by weight+0.2647×Ta % by weight  (1) MoEq−Mo % by weight+0.5217×W % by weight+0.5303×Ta % by weight+1.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yoshinari, Hideki Tamaki, Hiroyuki Doi
  • Publication number: 20040221925
    Abstract: A Ni-based alloy hardened with the &ggr;′ phase, which is able to exhibit not only superior strength at high temperatures, but also excellent hot corrosion resistance and oxidation resistance at high temperatures in spite of containing no Re or reducing the amount of Re. The Ni-based superalloy contains, by weight, C:0.01 to 0.5%, B:0.01 to 0.04%, Hf:0.1 to 2.5%, Co:0.8 to 15%, Ta:more than 0% but less than 8.5%, Cr:1.5 to 16%, Mo:more than 0% but less than 1.0%, W:5 to 14%, Ti:0.1 to 4.75%, Al:2.5 to 7%, Nb:more than 0% but less than 4%, V:0 to less than 1.0%, Zr:0 to less than 0.1%, Re:0 to less than 9%, at least one of platinum group elements: 0 to less than 0.5% in total, at least one of rare earth elements: 0 to less than 0.1% in total, and the rest being Ni except for unavoidable impurities.
    Type: Application
    Filed: March 19, 2004
    Publication date: November 11, 2004
    Inventors: Hideki Tamaki, Akira Yoshinari, Akira Okayama, Tsuyoshi Takano, Hiroyuki Doi
  • Publication number: 20040177901
    Abstract: A nickel-based superalloy containing 12.0 to 16.0% by weight of Cr, 4.0 to 9.0% by weight of Co, 3.4 to 4.6% by weight of Al, 0.5 to 1.6% by weight of Nb, 0.05 to 0.16% by weight of C, 0.005 to 0.025% by weight of B, and at least one of Ti, Ta and Mo. Amounts of Ti, Ta and Mo are ones calculated by the equations (1) and (2), wherein TiEq is 4.0 to 6.0 and MoEq is 5.0 to 8.0.
    Type: Application
    Filed: May 6, 2003
    Publication date: September 16, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Akira Yoshinari, Hideki Tamaki, Hiroyuki Doi
  • Patent number: 6784520
    Abstract: A constant voltage device includes n-type and p-type doped layers. The n-type doped layer is formed by heavily doping with an n-type impurity an upper portion of a p-type silicon semiconductor substrate, in an active region defined by an isolating insulator film. The p-type doped layer is formed by doping the region under the n-type doped layer with a p-type impurity. The n-type and p-type doped layers are provided to form two layers in parallel with the substrate surface of the semiconductor substrate, whereby a pn junction formed between the n-type and p-type doped layers creates a diode structure. Impurity concentration in the p-type doped layer is established so that the impurity concentration of a portion adjacent the isolating insulator film is lower that that of the rest.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Doi
  • Patent number: 6773992
    Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Doi
  • Publication number: 20040149735
    Abstract: An induction heating roller device that keeps leakage current within specifications and prevents the occurrence of erroneous operations caused by common mode noise. The induction heating roller device includes an induction coil, a grounded heating roller magnetically coupled to the induction coil and heated by electro-magnetic induction. A power factor improving capacitor is connected in parallel to and near the induction coil and has a grounded intermediate point. A high-frequency power source biases the induction coil. The leakage current produced by distributed capacitance between the induction coil and the heating roller is returned to the high-frequency power source via the power factor improving capacitor. Thus, the leakage current does not flow out of the induction heating roller device.
    Type: Application
    Filed: December 11, 2003
    Publication date: August 5, 2004
    Inventors: Takayuki Ogasawara, Hiroyuki Doi, Ichiro Yokozeki, Manabu Kika, Toshiya Suzuki, Takaaki Tanaka, Syouhei Maeda
  • Publication number: 20040129696
    Abstract: An induction heating roller device that reduces noise emission to the outside and facilitates insulating between induction coils and nearby metal materials. The induction heating roller device includes a heating roller, a plurality of induction coils arranged in the axial direction of the heating roller, and a high-frequency power source for supplying high-frequency power to the plurality of induction coils. The high-frequency power source has a first output terminal set at a stable potential, and a second output terminal set at a non-stable potential. A pair of induction coils are arranged at the ends of the heating roller and a first end of the coils is positioned at the end of the heating roller and a second end of the coils is positioned in the central side of the heating roller. The first end of each of the two induction coils is connected to the first output terminal, and the second end of each of the two induction coils is connected to the second output terminal.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 8, 2004
    Inventors: Hiroyuki Doi, Ichiro Yokozeki, Manabu Kika, Takayuki Ogasawara, Toshiya Suzuki, Takaaki Tanaka, Syouhei Maeda
  • Patent number: 6753222
    Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda
  • Publication number: 20040075296
    Abstract: The present invention provides a structural member for a car capable of demonstrating excellent flexural strength and absorbed energy performance and, moreover, capable of realizing weight reduction and is a structural member for a car being formed with a high-tensile steel pipe having a material property of not less than 1,400 MPa in tensile strength and not less than 5% in elongation, and also having a closed section structure as the configuration of the cross section perpendicular to the direction of the longitudinal axis, the cross-sectional configuration satisfying the expression (1) below when defining a as the maximum length of said cross-sectional configuration in the longitudinal direction, when defining b as the maximum length thereof in the direction perpendicular to said direction, when defining L as the circumferential length thereof and when defining t as the wall thickness of the steel pipe,
    Type: Application
    Filed: August 26, 2003
    Publication date: April 22, 2004
    Inventors: Hiroyuki Doi, Takashi Motoyoshi, Tsutomu Takachi, Masanobu Kawase, Nobuyasu Yamada
  • Publication number: 20040076540
    Abstract: A welding material composition, which is a nickel based super alloy having &ggr;′ phase and chromium carbides precipitated. The composition comprising 18 to 25% by weight of Co, 15 to 20% by weight of Cr, 1.5 to 5.5% by weight of Al, 5 to 14% by weight of W, 0.05 to 0.15% by weight of C, 0 to 0.02% by weight of B, 0 to 1% by weight of at least one of Ta, Nb, Ti, Mo, Re and Fe, 0 to 0.5% by weight of at least one of V, Zr, rare earth elements and Y, 0 to 1% by weight of Mn, 0 to 0.5% by weight of Si, and the balance being Ni.
    Type: Application
    Filed: August 7, 2003
    Publication date: April 22, 2004
    Inventors: Shinya Imano, Hiroyuki Doi, Kunihiro Ichikawa, Hideaki Ishii
  • Patent number: 6700332
    Abstract: An electrodeless discharge lamp system includes an excitation coil placed in proximity of the electrodeless discharge lamp, a resonance circuit for supplying appropriate power to the excitation coil, and a high frequency power source driver and wherein, the combined output is achieved by operating the parallel connected power sources in synchronization or approximately in synchronization with each other.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: March 2, 2004
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Ichiro Yokozeki, Hiroyuki Doi, Takashi Terai, Ioshiya Suzuki, Masaaki Kawamura
  • Patent number: 6686641
    Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: February 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirotsugu Honda, Hiroyuki Doi, Katsujirou Arai, Takuo Akashi, Naritsugu Yoshii
  • Patent number: 6657893
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Publication number: 20030197206
    Abstract: A constant voltage device includes n-type and p-type doped layers. The n-type doped layer is formed by heavily doping with an n-type impurity an upper portion of a p-type silicon semiconductor substrate, in an active region defined by an isolating insulator film. The p-type doped layer is formed by doping the region under the n-type doped layer with a p-type impurity. The n-type and p-type doped layers are provided to form two layers in parallel with the substrate surface of the semiconductor substrate, whereby a pn junction formed between the n-type and p-type doped layers creates a diode structure. Impurity concentration in the p-type doped layer is established so that the impurity concentration of a portion adjacent the isolating insulator film is lower that that of the rest.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 23, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Hiroyuki Doi
  • Patent number: 6589197
    Abstract: A medical fluid passage switching apparatus comprising: at least, a rotatable shaft F; a cam C which is rotated in relation to the rotating movement of the shaft F to close and open divided tubes for determining a passage of a fluid; and a housing L having tube accepting holes I and so arranged to enable the holding of the cam C, is provided. More particularly, provided are such a medical fluid passage switching apparatus in a continuous ambulatory peritoneal dialysis (CAPD) system and a tube which is decreased in the diameter and/or thinned in the wall at a region where the cam or a combination of the cam and the clamp is engaged for closing and opening.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: July 8, 2003
    Assignee: JMS Co., Ltd.
    Inventors: Hiroyuki Doi, Kazuhiro Shinmoto, Zyunya Fujii, Seishin Tanaka
  • Publication number: 20030082878
    Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.
    Type: Application
    Filed: October 15, 2002
    Publication date: May 1, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda
  • Publication number: 20030036234
    Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.
    Type: Application
    Filed: April 11, 2002
    Publication date: February 20, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Hiroyuki Doi
  • Patent number: 6493936
    Abstract: A steam turbine blade made of Ti-base alloy comprising an &agr;+&bgr; type phase in which a difference of a tensile strength is small between a blade portion and a dovetail portion, a tensile strength at a room temperature of the dovetail portion is equal to or more than 100 kg/mm2 and a suitable toughness is commonly provided together with a strength, as a steam turbine blade having a length of 43 inch or more, a method of manufacturing the same, a steam turbine power generating plant and a low pressure steam turbine.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: December 17, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Doi, Mitsuo Kuriyama, Shigeyoshi Nakamura, Shinya Imano, Takeshi Onoda
  • Patent number: 6472281
    Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Doi, Yasushi Okuda, Keita Takahashi, Nobuyuki Tamura