Abstract: An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

Abstract: A sheet feeding apparatus includes an endless belt which is postioned to be adjacent to a rear part of a sheet stand on which trailing edges of a pile of sheets are loaded. The endless belt includes a holding member to hold a leading edge of a sheet that is being returned to the sheet stand so that the endless belt conveys the sheet together with the holding member and inserts the sheet being returned to the sheet stand under the pile of sheets. A single stopper is provided on the sheet stand to align the sheets of the pile as well as the sheets inserted under the pile.

Abstract: A cell library for a semiconductor integrated circuit design, comprises a CMOS cell comprising two power source wires and a CMOS circuit placed between the two power source wires at a predetermined distance, and a BiCMOS cell comprising two power source wires which are placed at a distance equal to the distance between the power source wires in the CMOS cell, a CMOS circuit placed between the two power source wires in the BiCMOS cell, and bipolar transistor circuits placed at both outsides of the two power source wires in the BiCMOS cell.

Abstract: An automatic document conveying device has a stack tray on which a plurality of documents are stacked; a feeder by which the documents stacked on the stack tray are separated and fed one by one; at least one pair of conveying rollers provided downstream of the feeder; a reading position for reading document information from said separated documents positioned downstream of the at least one pair of conveying rollers; a conveyor provided opposite to the reader for conveying separated documents to the reading position; a discharger positioned downstream of said reading position for discharging documents after said conveyor conveys the documents to the reading position, a conveyance path on which a plurality of documents are sequentially located between the feeder and the reading position; the conveyance path having predetermined stand-by positions provided on the conveyance path at which documents, subsequent to a document positioned at the reading position are stopped; a document detector provided between the a

Abstract: An input terminal IN is connected to the input of a CMOS inverter, and also to the gate of an N-channel MOS transistor N10. The output of the CMOS inverter is coupled to the base of an NPN transistor Q11 used for pulling up the output terminal OUT. The drain of the transistor N10 is connected to the input of a CMOS inverter. The output of the inverter is connected to the base of an NPN transistor Q12 used for pulling down the output terminal OUT. The emitter of the transistor Q11 and the collector of the transistor Q12 are connected to an output terminal OUT, which is coupled to the gate of a P-channel MOS transistor P12 and the gate of an N-channel MOS transistor N3. The drain of the transistor P12 is connected to the drain of the transistor N10. The drain of the transistor N13 is connected to the source of the transistor N10. The transistors N10, P12, and N13 constitute a circuit for controlling the CMOS inverter.

Abstract: A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array includes amplifying means constituted by a bipolar transistor connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means amplifies the potential level of readout data of the memory cell and output the same to an output line, thus enhancing the driving ability of the output line and reducing the whole readout time for reading out data from the memory circuit.

Abstract: A bipolar transistor/insulated gate transistor hybrid semiconductor device comprises a well region formed on a semiconductor substrate to serve as a first active region of a bipolar transistor, an insulated gate transistor having source and drain regions formed in the well region, which acts as a back gate of the insulated gate transistor, and second and third active regions of the bipolar transistor formed in the well region. At least one of the second and third active regions is used in common to one of the source and drain regions of the insulated gate transistor. A plurality of well regions is regularly arranged to constitute a gate array.

Abstract: In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node.

Abstract: In a sampled data transmitting apparatus in which the sampled data to be transmitted are divided into odd-numbered samples and even-numbered samples and arranged in different rows of a two-dimensional data array, and in which error correction codes are annexed to each row and to each column of the two-dimensional data array, the row arraying sequence in one of the odd-numbered or even-numbered rows is caused to differ from the row arraying sequence in the other of the odd-numbered or even-numbered rows so that odd-numbered data and even-numbered data continuous with the odd-numbered data are not arranged in one row. In this manner, even when error correction becomes impossible by the error correcting code for one row, interpolation remains feasible because there exist no odd-numbered data or even-numbered data contiguous to each other in the row.

Abstract: The invention is directed to a thermal cycle adhesion additive composition consisting essentially of an admixture of finely divided particles of oxides of bismuth, copper, lead, zinc, and transition metal and to conductive thick film compositions made therefrom.

Abstract: The present invention relates to a dry etching method in which the type of reactive gas used is improved and the selectively between a workpiece being etched and a substance below the workpiece is increased. A gas comprising a fluoride gas and a compound gas containing hydrogen as a constituent element is used as the reactive gas. According to the present invention, the etching selectivity between a workpiece being etched and a substance below the workpiece is greatly increased, and etching of the substance below the workpiece can be prevented.The present invention is applicable to a semiconductor structure having a silicon oxide film below a silicon nitride film.

Abstract: In a Bi-CMOS output circuit constituted by combining a bipolar transistor and a CMOS circuit, in an output circuit obtained by connecting current paths of two bipolar transistors in series between a power source and ground, when the bipolar transistor connected to ground is driven by a bipolar transistor, an output current value can be assured when an output voltage is low. However, when the output voltage is high, a large current is supplied to the bipolar transistor to vary a power source voltage. Therefore, the output terminal of the MOS transistor is connected through a resistor to the grounded control signal input terminal of the bipolar transistor. Since the bipolar transistor connected to the ground is driven by a MOS transistor having drivability lower than that of a normal bipolar transistor, when the output voltage is low, a predetermined current can be assured. When the output voltage is high, supply of a large current can be prevented.

Abstract: A P-channel MOSFET includes a gate for receiving an input signal, a source connected to a power supply terminal to which a high power supply voltage is applied, and a drain connected to the base of an NPN bipolar transistor at an output stage. The collector of the bipolar transistor is connected to the power supply terminal and the emitter thereof is connected to an output terminal. An N-channel MOSFET includes a gate for receiving the input signal, a drain connected to the output terminal, and a source and a back gate both connected to the base of an NPN bipolar transistor at the output stage. The collector of the bipolar transistor is connected to the output terminal, and the emitter thereof is connected to a power supply terminal to which a power supply voltage of ground potential is applied.

Abstract: A semiconductor integrated circuit includes a bias voltage generating circuit and first- and second-level signal generating circuits. The bias voltage generating circuit includes a bandgap reference circuit for generating a first fixed voltage as a first bias voltage and a second fixed voltage. A second bias voltage is generated on the basis of the second fixed voltage. The second-level signal generating circuit receives a predetermined first-level signal and generates a predetermined second-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit. The first-level signal generating circuit receives the predetermined second-level signal and generates the predetermined first-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit.

Abstract: A semiconductor device is disclosed having a channelless gate array. A plurality of standard cells are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor and resistor shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.

Abstract: A gate array semiconductor integrated circuit includes a plurality of input/output cells, an input/output circuit, and a bias circuit. The plurality of input/output cells are arranged around an internal logic gate. The input/output circuit is formed by an aluminum master slice of the input/output cells and performs an input/output operation for the internal logic gate. The bias circuit is formed by the aluminum master slice of the input/output cells to supply a predetermined bias voltage to the input/output circuit.

Abstract: A complementary signal output circuit for supplying an in-phase and an anti-phase output signal in response to an input signal. The falling of the in-phase signal from a high to a low level and the rising of the anti-phase signal from a low to a high level are both controlled in a manner which serves to speed up the output of the anti-phase signal and reduce skew between the complementary signals. This is accomplished by providing a number of inverter means, and transistor means which outputs a low-to-high signal to the anti-phase output in response to the inverted input signal. Additional circuitry responsive to the input signal is used to prevent undesired current from flowing through the transistor and inverter means.

Abstract: To provide a high-speed wide-dynamic range differential amplifier, the amplifier comprises first and second FETs having source terminals connected to each other and a constant current source connected between the sources and ground; third and fourth bipolar transistors complementary to the first and second FETs, having base terminals connected to a first bias voltage in common and emitter terminals connected to the drains of the first and second FETs and a supply voltage via resistors, respectively; and a current mirror circuit composed of fifth and sixth FETs of the same conductive type as the first and second FETs.

Abstract: A logic operation circuit includes an exclusive-OR circuit for receiving first and second logic sum signals of preceeding stages, a sum signal selection circuit for selectively generating a carry output signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating the carry input signal or the first logic sum signal as a sum signal in accordance with the output signal from the exclusive-OR circuit. The exclusive-OR circuit includes a double balance type differential amplifier connected between first and second power source terminals, and the sum signal selection circuit includes a double balance differential amplifier operated in accordance with the output signal from the exclusive-OR circuit and the carry input signal and connected between the first and second power source terminals.

Abstract: A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.