Abstract: Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.

Abstract: A tri-state buffer circuit according to the present invention comprises a switching circuit connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have a first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal; an inverter circuit connected to said switching circuit, and the first power supply terminal for inverting the first switching signal (A) from said switching circuit as an output signal; a selection circuit connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; a first type bipolar transistor whose base is connected to said inverter circuit, whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of t

Abstract: A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit.

Abstract: A voltage level converting circuit includes first and second potential terminals between which a power source voltage is applied, first and second terminals for receiving an input signal and an inverted input signal, a differential amplifier including npn transistors whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier. The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals by way of a constant current source, and includes a MOS transistor whose conduction state is controlled by the output voltage of the differential amplifier.