Patents by Inventor Hiroyuki Kamiya
Hiroyuki Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12101928Abstract: A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer.Type: GrantFiled: August 30, 2021Date of Patent: September 24, 2024Assignee: KIOXIA CORPORATIONInventors: Natsuki Fukuda, Ryota Narasaki, Takashi Kurusu, Yuta Kamiya, Kazuhiro Matsuo, Shinji Mori, Shoji Honda, Takafumi Ochiai, Hiroyuki Yamashita, Junichi Kaneyama, Ha Hoang, Yuta Saito, Kota Takahashi, Tomoki Ishimaru, Kenichiro Toratani
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Patent number: 12067413Abstract: One or more storage devices store resource migration schedule information including a plurality of records. Each of the plurality of records indicating a migration source node and a migration destination node of each of one or more resources. One or more processors are configured to determine a priority of each of the plurality of records such that a record having locality after migration has a higher priority than a priority of a record without locality after migration. The locality is determined based on whether a virtual machine and a volume associated with each other in advance exist in the same node. The one or more processors are configured to determine a migration schedule of each of the plurality of records based on the priority of each of the plurality of records.Type: GrantFiled: September 9, 2021Date of Patent: August 20, 2024Assignee: HITACHI, LTD.Inventors: Yuushi Kamiya, Hiroyuki Morimoto, Hideo Saito
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Publication number: 20230138940Abstract: To provide hollow silica particles having a dense silica shell layer. A method for producing hollow silica particles, which comprises: adjusting the pH of an oil-in-water emulsion containing an aqueous phase, an oil phase and a surfactant to at most 3.0 and adding a first silica material to the oil-in-water emulsion, adding a second silica material to the emulsion having the first silica material added, at its pH of at least 8, in the presence of alkali metal ions, to obtain a hollow silica precursor dispersion, and obtaining a hollow silica precursor from the hollow silica precursor dispersion and obtaining hollow silica particles from the hollow silica precursor.Type: ApplicationFiled: December 29, 2022Publication date: May 4, 2023Applicants: AGC Inc., AGC Si-Tech Co., Ltd.Inventors: Hiroyuki KAMIYA, Hyunji KIM, Toshiya MATSUBARA
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Patent number: 11608273Abstract: To provide hollow silica particles having a dense silica shell layer. A method for producing hollow silica particles, which comprises: adjusting the pH of an oil-in-water emulsion containing an aqueous phase, an oil phase and a surfactant to at most 3.0 and adding a first silica material to the oil-in-water emulsion, adding a second silica material to the emulsion having the first silica material added, at its pH of at least 8, in the presence of alkali metal ions, to obtain a hollow silica precursor dispersion, and obtaining a hollow silica precursor from the hollow silica precursor dispersion and obtaining hollow silica particles from the hollow silica precursor.Type: GrantFiled: May 28, 2020Date of Patent: March 21, 2023Assignees: AGC Inc., AGC Si-Tech Co., Ltd.Inventors: Hiroyuki Kamiya, Hyunji Kim, Toshiya Matsubara
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Three-dimensional memory device containing a channel connection strap and method for making the same
Patent number: 11171150Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.Type: GrantFiled: March 7, 2019Date of Patent: November 9, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Yuda, Hiroyuki Kamiya -
Publication number: 20200283300Abstract: To provide hollow silica particles having a dense silica shell layer. A method for producing hollow silica particles, which comprises: adjusting the pH of an oil-in-water emulsion containing an aqueous phase, an oil phase and a surfactant to at most 3.0 and adding a first silica material to the oil-in-water emulsion, adding a second silica material to the emulsion having the first silica material added, at its pH of at least 8, in the presence of alkali metal ions, to obtain a hollow silica precursor dispersion, and obtaining a hollow silica precursor from the hollow silica precursor dispersion and obtaining hollow silica particles from the hollow silica precursor.Type: ApplicationFiled: May 28, 2020Publication date: September 10, 2020Applicants: AGC Inc., AGC Si-Tech Co., Ltd.Inventors: Hiroyuki KAMIYA, Hyunji KIM, Toshiya MATSUBARA
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THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CHANNEL CONNECTION STRAP AND METHOD FOR MAKING THE SAME
Publication number: 20200286909Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Takashi YUDA, Hiroyuki KAMIYA -
Patent number: 10625776Abstract: The invention relates to a driving assistant adapted for active control of a vehicle based on predictions of a behavior of a detected object. A method aspect of the invention comprises accepting a first prediction of a behavior associated with the detected object from a first prediction subsystem and a second prediction from a second prediction subsystem; determining a control signal based on a combination of the first prediction and the second prediction; and initiating active control of the vehicle based on the control signal.Type: GrantFiled: September 5, 2014Date of Patent: April 21, 2020Assignee: HONDA RESEARCH INSTITUTE EUROPE GMBHInventors: Sven Rebhan, Jens Schmüdderich, Marcus Kleinehagenbrock, Robert Kastner, Naoki Mori, Shunsuke Kusuhara, Hiroyuki Kamiya
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Patent number: 10354859Abstract: An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.Type: GrantFiled: March 14, 2018Date of Patent: July 16, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Hiroyuki Kamiya, Shigehisa Inoue, Seiji Shimabukuro
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Patent number: 9793288Abstract: Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.Type: GrantFiled: December 4, 2014Date of Patent: October 17, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Shinsuke Yada, Hiroyuki Kamiya
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Patent number: 9553100Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.Type: GrantFiled: December 4, 2014Date of Patent: January 24, 2017Assignee: SANDISK TECHOLOGIES LLCInventors: Hiroyuki Kamiya, Kensuke Yamaguchi
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Lane outward deviation avoidance assist apparatus and lane outward deviation avoidance assist method
Patent number: 9511768Abstract: A lane outward deviation avoidance assist apparatus includes: a recognition device configured to recognize a travel lane of a vehicle; a deviation recognition part configured to recognize a deviation from the travel lane recognized by the recognition device or a deviation prediction from the travel lane; a control part configured to perform a deviation avoidance control for avoiding the deviation from the travel lane at least by a steering; and a deviation number count part configured to count the number of deviations from the travel lane recognized by the deviation recognition part within a predetermined duration or the number of deviation predictions from the travel lane, wherein the control part performs at least any one of the deviation avoidance control and an alarm output control when the number counted by the deviation number count part reaches n, n being a natural number more than 1.Type: GrantFiled: April 1, 2015Date of Patent: December 6, 2016Assignee: Honda Motor Co., Ltd.Inventors: Makoto Ito, Shinnosuke Ishida, Kentaro Yamada, Daisuke Hanzawa, Hiroyasu Kubota, Hiroyuki Kamiya -
Patent number: 9501935Abstract: In an intelligent forward collision warning system that takes into account not only a first preceding vehicle traveling immediately ahead of the ego vehicle but also a second preceding vehicle traveling immediately ahead of the first preceding vehicle, a warning signal is produced upon detecting a critical state of the first or second preceding vehicle or an external condition that is predicted to cause the first preceding vehicle and the ego vehicle to be in a same lane with the first time to collision (TTC) below a prescribed value.Type: GrantFiled: July 17, 2014Date of Patent: November 22, 2016Assignee: Honda Motor Co., Ltd.Inventors: Robert Kastner, Marcus Kleinehagenbrock, Morimichi Nishigaki, Hiroyuki Kamiya, Shunsuke Kusuhara, Naoki Mori, Jens Schmudderich, Sven Rebhan
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Publication number: 20160181271Abstract: Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.Type: ApplicationFiled: December 4, 2014Publication date: June 23, 2016Inventors: Shinsuke YADA, Hiroyuki KAMIYA
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Publication number: 20160163725Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.Type: ApplicationFiled: December 4, 2014Publication date: June 9, 2016Inventors: Hiroyuki KAMIYA, Kensuke YAMAGUCHI
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LANE OUTWARD DEVIATION AVOIDANCE ASSIST APPARATUS AND LANE OUTWARD DEVIATION AVOIDANCE ASSIST METHOD
Publication number: 20150307094Abstract: A lane outward deviation avoidance assist apparatus includes: a recognition device configured to recognize a travel lane of a vehicle; a deviation recognition part configured to recognize a deviation from the travel lane recognized by the recognition device or a deviation prediction from the travel lane; a control part configured to perform a deviation avoidance control for avoiding the deviation from the travel lane at least by a steering; and a deviation number count part configured to count the number of deviations from the travel lane recognized by the deviation recognition part within a predetermined duration or the number of deviation predictions from the travel lane, wherein the control part performs at least any one of the deviation avoidance control and an alarm output control when the number counted by the deviation number count part reaches n, n being a natural number more than 1.Type: ApplicationFiled: April 1, 2015Publication date: October 29, 2015Inventors: Makoto ITO, Shinnosuke ISHIDA, Kentaro YAMADA, Daisuke HANZAWA, Hiroyasu KUBOTA, Hiroyuki KAMIYA -
Publication number: 20150073662Abstract: The invention relates to a driving assistant adapted for active control of a vehicle based on predictions of a behavior of a detected object. A method aspect of the invention comprises accepting a first prediction of a behavior associated with the detected object from a first prediction subsystem and a second prediction from a second prediction subsystem; determining a control signal based on a combination of the first prediction and the second prediction; and initiating active control of the vehicle based on the control signal.Type: ApplicationFiled: September 5, 2014Publication date: March 12, 2015Inventors: Jens Schmüdderich, Sven Rebhan, Marcus Kleinehagenbrock, Robert Kastner, Naoki Mori, Shunsuke Kusuhara, Hiroyuki Kamiya
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Publication number: 20150025784Abstract: In an intelligent forward collision warning system that takes into account not only a first preceding vehicle traveling immediately ahead of the ego vehicle but also a second preceding vehicle traveling immediately ahead of the first preceding vehicle, a warning signal is produced upon detecting a critical state of the first or second preceding vehicle or an external condition that is predicted to cause the first preceding vehicle and the ego vehicle to be in a same lane with the first time to collision (TTC) below a prescribed value.Type: ApplicationFiled: July 17, 2014Publication date: January 22, 2015Inventors: Robert KASTNER, Marcus KLEINEHAGENBROCK, Morimichi NISHIGAKI, Hiroyuki KAMIYA, Shunsuke KUSUHARA, Naoki MORI, Jens SCHMUDDERICH, Sven REBHAN
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Patent number: 8304346Abstract: The present invention relates to a polishing composition used in a step of polishing until a barrier layer adjacent to a copper layer is exposed, in a pattern formation of polishing the copper layer provided on an insulating layer through the barrier layer thereby alternately forming a copper embedded wiring and the insulating layer, the polishing composition including: an alicyclic resin acid; a colloidal silica in which a content thereof in the polishing composition is from 0.1 to 1.5% by mass, an average primary particle size thereof is from 10 to 40 nm, an average secondary particle size thereof is from 30 to 80 nm, and (the average secondary particle size×the content) is in a range of from 10 to 40; and tetramethylammonium ion.Type: GrantFiled: May 5, 2011Date of Patent: November 6, 2012Assignee: Asahi Glass Company, LimitedInventors: Iori Yoshida, Hiroyuki Kamiya
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Publication number: 20110212621Abstract: The present invention relates to a polishing composition used in a step of polishing until a barrier layer adjacent to a copper layer is exposed, in a pattern formation of polishing the copper layer provided on an insulating layer through the barrier layer thereby alternately forming a copper embedded wiring and the insulating layer, the polishing composition including: an alicyclic resin acid; a colloidal silica in which a content thereof in the polishing composition is from 0.1 to 1.5% by mass, an average primary particle size thereof is from 10 to 40 nm, an average secondary particle size thereof is from 30 to 80 nm, and (the average secondary particle size×the content) is in a range of from 10 to 40; and tetramethylammonium ion.Type: ApplicationFiled: May 5, 2011Publication date: September 1, 2011Applicant: Asahi Glass Company, LimitedInventors: Iori YOSHIDA, Hiroyuki Kamiya