Patents by Inventor Hiroyuki Minemura
Hiroyuki Minemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170160185Abstract: An objective of the present invention is to provide a technique for reducing measurement errors when measuring specimen using light. An aspect of an optical measurement method according to the present invention: acquires relationship data that describes a relationship between an intensity of reflection light when irradiating light onto a specimen and a size of the specimen; and acquires the size of the specimen using the relationship data and the intensity of the reflection light. Another aspect of an optical measurement method according to the present invention subtracts a component due to an inclination of a vessel of a specimen from a detection signal representing an intensity of reflection light when irradiating light onto the specimen, thereby correcting the inclination of the vessel.Type: ApplicationFiled: November 15, 2016Publication date: June 8, 2017Inventors: Hiroyuki MINEMURA, Kentaro OSAWA, Yumiko ANZAI
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Publication number: 20170059300Abstract: Provided is an optical measuring device that can realize a wide measurement region without an increase in the measurement time or a reduction in the measurement region while avoiding damage to a measurement target due to excessive light exposure, using a simple configuration. The device includes a light source, an optical splitting unit configured to split a light beam emitted from the light source into a signal beam and a reference beam, an objective lens configured to focus the signal beam and irradiate a measurement target with the signal beam, a scanning unit configured to move the focus position of the signal beam, an optical element having lower transmissivity in its peripheral portion than in its central portion, interference optics configured to combine the reference beam with the signal beam reflected or scattered by the measurement target, thereby generating interference beams, and photodetectors configured to detect the respective interference beams.Type: ApplicationFiled: July 13, 2016Publication date: March 2, 2017Inventors: Kentaro OSAWA, Hiroyuki MINEMURA, Yumiko ANZAI
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Patent number: 9557462Abstract: A technology that allows improvement in the performance of an optical element a representative example of which is a polarizing element is provided. In a split wire element according to an embodiment of the invention, each of a plurality of split wires (SPW) has gaps formed in a y direction at a period ?, and the period ? is greater than or equal to a Rayleigh wavelength (?/n). According to the thus configured split wire element of the embodiment of the invention, optical performance can be improved as compared with a wire-grid element formed of straight wires having no periodic structure in the y direction.Type: GrantFiled: February 26, 2014Date of Patent: January 31, 2017Assignee: HITACHI MAXELL, LTD.Inventors: Hiroyuki Minemura, Yumiko Anzai
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Patent number: 9478284Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).Type: GrantFiled: May 20, 2013Date of Patent: October 25, 2016Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Kenzo Kurotsuchi, Seiji Miura, Satoru Hanzawa
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Publication number: 20160265899Abstract: By utilizing the fact that the observation object has a three-dimensional shape and the boundary surface can be regarded as a plane surface, phase or intensity distribution is applied into a luminous flux of reference light, thereby selectively attenuating the influence of the reflected light from the boundary surface so as to obtain a high-quality OCT image.Type: ApplicationFiled: January 8, 2016Publication date: September 15, 2016Inventors: Hiroyuki Minemura, Kentaro Osawa
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Publication number: 20160078932Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).Type: ApplicationFiled: May 20, 2013Publication date: March 17, 2016Inventors: Yoshitaka SASAGO, Hiroyuki MINEMURA, Kenzo KUROTSUCHI, Seiji MIURA, Satoru HANZAWA
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Publication number: 20150234230Abstract: In order to improve a characteristic of an optical element, an optical element (polarizing filter) including a substrate 1S having a wire-grid region 1A and a peripheral region 2A positioned on an outer periphery thereof is made to have the following configuration. A wire-grid in which a plurality of line-shaped wires P10 made of Al and extending in a y direction are arranged at spaces S in an x direction is provided in the wire-grid region 1A of the substrate 1S, and a pattern (repetitive pattern) in which a plurality of protruding portions P20 made of Al are arranged is provided in the peripheral region 2A. This pattern is, for example, a checkerboard pattern. According to the above-mentioned configuration, the plurality of wires P10 can be arranged so that their respective ends are spaced apart from an end of the substrate 1S, so that the wires P10 can be prevented from being deformed and nicked.Type: ApplicationFiled: June 21, 2012Publication date: August 20, 2015Inventors: Koji Hirata, Hiroyuki Minemura, Yumiko Anzai, Tetsuya Nishida, Jiro Yamamoto, Naoyuki Kofuji, Hidehiro Ikeda, Nobuyuki Kimura
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Publication number: 20150226896Abstract: Provided are an optical element and an optical device using the optical element to which a manufacturing process for manufacturing a wire-grid structure can be basically applied, and besides, in which a higher polarization contrast ratio than that of a wire-grid element can be obtained. A wobbled wire element in an embodiment has a feature that a periodic structure having a period equal to or larger than a wavelength of an incident light wave is formed in a y direction. In this manner, in a wobbled wire element in a first embodiment, a polarization contrast ratio can be significantly improved.Type: ApplicationFiled: June 21, 2012Publication date: August 13, 2015Inventors: Koji Hirata, Hiroyuki Minemura, Yumiko Anzai, Tetsuya Nishida, Jiro Yamamoto, Naoyuki Kofuji, Hidehiro Ikeda, Nobuyuki Kimura
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Patent number: 8997615Abstract: A microtome comprising a head 32 which holds a sample, an alignment mechanism 50 which aligns the head 32, a body portion 42 which is provided on a back face side of the alignment mechanism 50, a cylindrical coupling portion 41 which couples the body portion 42 with the head 32, a temperature controller 34 in the head 32, and refrigerant piping 40 and electrical wiring 46 for the temperature controller 34, and the alignment mechanism 50 includes a spherical member 68 coupled with the back face side of the head and having a spherical outer periphery and includes retainer portions 70 and 71 retaining the outer periphery of the spherical member 68 slidably along a spherical surface, the spherical member 68 has a through hole 74 which communicates with the hollow portion 43 of the coupling portion 41, the refrigerant piping 40 and the electrical wiring 46 are connected with the temperature controller 34 in the head 32 through the through hole 74 of the spherical member 68 and the hollow portion 43 of the couplingType: GrantFiled: July 29, 2011Date of Patent: April 7, 2015Assignees: Sakura Seiki Co., Ltd., Sakura Finetek Japan Co., Ltd.Inventors: Hiroyuki Minemura, Tatsuya Seki
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Patent number: 8891168Abstract: The present invention provides a small and inexpensive optical element that integrates a reflecting mirror and a wave plate function. A reflecting wave plate is configured by arranging a periodic metal comb-like structure whose pitch is equal to or below a wavelength and a mirror structure with a distance equal to or below a coherence length.Type: GrantFiled: October 4, 2010Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Hiroyuki Minemura, Yumiko Anzai, Hideharu Mikami
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Publication number: 20140293195Abstract: A technology that allows improvement in the performance of an optical element a representative example of which is a polarizing element is provided. In a split wire element according to an embodiment of the invention, each of a plurality of split wires (SPW) has gaps formed in a y direction at a period ?, and the period ? is greater than or equal to a Rayleigh wavelength (?/n). According to the thus configured split wire element of the embodiment of the invention, optical performance can be improved as compared with a wire-grid element formed of straight wires having no periodic structure in the y direction.Type: ApplicationFiled: February 26, 2014Publication date: October 2, 2014Applicant: Hitachi Maxell, Ltd.Inventors: Hiroyuki MINEMURA, Yumiko ANZAI
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Patent number: 8830740Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.Type: GrantFiled: August 26, 2011Date of Patent: September 9, 2014Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
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Patent number: 8743671Abstract: A recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on an acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum.Type: GrantFiled: April 3, 2013Date of Patent: June 3, 2014Assignee: Hitachi Consumer Electronics Co., Ltd.Inventors: Takahiro Kurokawa, Hiroyuki Minemura
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Patent number: 8735865Abstract: For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.Type: GrantFiled: January 8, 2011Date of Patent: May 27, 2014Assignee: Hitachi, Ltd.Inventors: Hiroyuki Minemura, Yumiko Anzai, Takahiro Morikawa, Toshimichi Shintani, Yoshitaka Sasago
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Patent number: 8658998Abstract: An intermediate layer including at least one of elements constituting a phase change material and silicon is arranged between a recording layer composed of the phase change material and an n+ polysilicon film to reduce contact resistance between the recording layer and the n+ polysilicon film, thereby simplifying the structure of a phase change memory and reducing the cost thereof. If the phase change material contains Ge, Sb, and Te, for example, the intermediate layer includes at least one of Si—Sb, Si—Te, and Si—Ge.Type: GrantFiled: April 27, 2012Date of Patent: February 25, 2014Assignee: Hitachi, Ltd.Inventors: Hiroyuki Minemura, Yumiko Anzai
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Patent number: 8642988Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.Type: GrantFiled: August 17, 2012Date of Patent: February 4, 2014Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi, Hiroyuki Minemura
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Patent number: 8634257Abstract: A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.Type: GrantFiled: May 8, 2012Date of Patent: January 21, 2014Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hiroyuki Minemura
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Publication number: 20130242714Abstract: A recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on an acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum.Type: ApplicationFiled: April 3, 2013Publication date: September 19, 2013Applicant: Hitachi Consumer Electronics Co. Ltd.Inventors: Takahiro Kurokawa, Hiroyuki Minemura
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Publication number: 20130242391Abstract: In a first face and a second face of an irregular configuration portion configuring a wire grid structure, surface roughness of the first face farther from an input side of a light (electromagnetic wave) is made rougher than the surface roughness of the second face closer to the input side of the light (electromagnetic wave). With this configuration, according to this embodiment, since a reflection polarization element can be realized, there can be provided an optical device that is excellent in tolerance to heat and light, and contributes to a reduction in the costs.Type: ApplicationFiled: February 4, 2013Publication date: September 19, 2013Applicant: HITACHI CONSUMER ELECTRONICS CO., LTD.Inventors: Hiroyuki MINEMURA, Yumiko ANZAI
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Patent number: 8531932Abstract: In a optical disc system with constraint length equal to or greater than 5, under assumption that continuous 2T count included in a predetermined evaluation bit array is denoted by i and that length of evaluation bit array of interest is given by (5+2i), judgment is passed on whether binary bit arrays include the evaluation bit array. Previously prepared are the error vectors calculated on the basis of target signals corresponding to the evaluation bit arrays and the target signals derived from the binary bit arrays, and the selection of a desired error vector is performed depending on the result of the judgment. At the same time, an equalized error vector is calculated from the target signal derived from the binary bit array and the reproduced signal, and the inner product of the equalized error vector and the selected error vector is calculated.Type: GrantFiled: October 29, 2009Date of Patent: September 10, 2013Assignee: Hitachi Consumer Electronics Co., Ltd.Inventors: Yusuke Nakamura, Koichiro Nishimura, Hiroyuki Minemura, Takahiro Kurokawa