Patents by Inventor Hiroyuki Minemura

Hiroyuki Minemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8483028
    Abstract: Provided is a recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on the acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 9, 2013
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Takahiro Kurokawa, Hiroyuki Minemura
  • Publication number: 20130141968
    Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
    Type: Application
    Filed: August 26, 2011
    Publication date: June 6, 2013
    Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
  • Publication number: 20130137163
    Abstract: Provided is a microtome in which refrigerant piping and electrical wiring are not impeditive so that cleaning and other works can be surely conducted.
    Type: Application
    Filed: July 29, 2011
    Publication date: May 30, 2013
    Applicants: SAKURA FINETEK JAPAN CO., LTD., SAKURA SEIKI CO., LTD.
    Inventors: Hiroyuki Minemura, Tatsuya Seki
  • Publication number: 20130075684
    Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.
    Type: Application
    Filed: August 17, 2012
    Publication date: March 28, 2013
    Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi, Hiroyuki Minemura
  • Publication number: 20120287697
    Abstract: A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 15, 2012
    Inventors: SATORU HANZAWA, Hiroyuki Minemura
  • Publication number: 20120273742
    Abstract: An intermediate layer including at least one of elements constituting a phase change material and silicon is arranged between a recording layer composed of the phase change material and an n+ polysilicon film to reduce contact resistance between the recording layer and the n+ polysilicon film, thereby simplifying the structure of a phase change memory and reducing the cost thereof. If the phase change material contains Ge, Sb, and Te, for example, the intermediate layer includes at least one of Si—Sb, Si—Te, and Si—Ge.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 1, 2012
    Inventors: Hiroyuki MINEMURA, Yumiko ANZAI
  • Patent number: 8289827
    Abstract: Recording parameters are decided so that the time control information on at least the front edge and the rear edge of a parameter forming a mark of twice size or above of the laser spot diameter focused on the recording medium is substantially proportional to the recording linear velocity. The mark is recorded and reproduced at a predetermined linear velocity to obtain an electric signal waveform having a time width Tm. A parameter is decided so as to control the laser pulse for recording information so that a voltage value change amount at two points at a distance Ts (Ts<Tm/2) in the time axis direction before and after the time position Tm/2 from the front edge of the waveform is substantially constant for the recording linear velocity change. Identification information indicating the parameter is described on the recording medium.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: October 16, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koichiro Nishimura, Masaaki Kurebayashi, Tsuyoshi Toda, Hiroyuki Minemura
  • Publication number: 20120250480
    Abstract: Provided is a recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on the acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum.
    Type: Application
    Filed: March 2, 2010
    Publication date: October 4, 2012
    Inventors: Takahiro Kurokawa, Hiroyuki Minemura
  • Patent number: 8264932
    Abstract: An optical disc device and an adjusting method for a recording condition for use with the optical disc device that records data into an optical disc medium by using codes whose shortest run length is 2T and reproduces the recorded data by using an adaptive equalizing procedure and a PRML procedure, wherein the recording condition is so adjusted that a reproduced signal with desired quality can be obtained, by using, as the adaptive equalizing procedure, a procedure in which a tap coefficient Cn is set to a value obtained by averaging values of a tap coefficient an renewed by a LMS method, located symmetrically with each other along the time axis.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: September 11, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Hiroyuki Minemura, Takahiro Kurokawa
  • Patent number: 8192700
    Abstract: The present invention can solve such a problem that a conventional tissue piece treating apparatus has difficulty of reduction in size and restriction on installation and stopping subsequent treatment operations when the amount of chemical supplied to a processing chamber is insufficient.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: June 5, 2012
    Assignees: Sakura Seiki Co., Ltd., Sakura Finetek Japan Co., Ltd.
    Inventor: Hiroyuki Minemura
  • Patent number: 8169866
    Abstract: By referring to a table of reproducing conditions and medium specific parameters, stored in an optical disc or optical disc apparatus and/or generated by the optical disc apparatus, the medium specific parameters to be used for performing reproducing power adjustment are changed in accordance with the reproducing condition to execute reproducing power adjustment.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 1, 2012
    Assignee: Hitachi Comsumer Electronics Co., Ltd.
    Inventors: Soichiro Eto, Toshimichi Shintani, Hiroyuki Minemura
  • Patent number: 8154973
    Abstract: A highly efficient and reliable reproduced signal evaluation method and an optical disc drive using that method in which assuming that the number of 2T's appearing successively in a predetermined evaluation bitstream is i, the evaluation bitstream is divided into a main bitstream (5+2i) long and sub bitstreams at the ends of the main bitstream. The check process to determine whether a predetermined evaluation bitstream is included in the binarized bitstreams is replaced with a main bitstream agreement check. This can prevent an increase in the circuit size. At the same time, by separately summing up for each main bitstream the calculated results of Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bitstream, the size of an evaluation summing circuit can be reduced.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 10, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Hiroyuki Minemura, Soichiro Eto, Takahiro Kurokawa, Shuichi Kusaba
  • Patent number: 8144559
    Abstract: Pulses modulated between the erase power and the bottom power are used instead of cooling pulses for an optical disk medium that needs a write strategy with 4-valued power levels. Consequently, pulse instruction lines for the cooling pulses, power level instruction lines, and corresponding current source within the laser driver can be omitted. Decrease in size and lower power consumption can be accomplished.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 27, 2012
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventors: Hiroyuki Minemura, Tsuyoshi Toda, Toshimitsu Kaku
  • Patent number: 8121226
    Abstract: A method and optical disc apparatus for evaluating a quality of a read signal adapted to the PRML method by evaluating a binary code decoded from the read signal obtained by a head, in which an error bit sequence having one bit edge shift from the binary code is generated, a Euclidian distance is calculated on both a correct bit sequence and the error bit sequence with respect to a predetermined target signal level, assuming that the binary code is the correct bit sequence, a Euclidian distance difference between the Euclidian distance on the correct bit sequence and the Euclidian distance on the error bit sequence is calculated, an average Euclidian distance from the target signal level is calculated, a normalized sequence error is calculated, the binary code is evaluated using the normalized sequence error.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: February 21, 2012
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventor: Hiroyuki Minemura
  • Patent number: 8121014
    Abstract: Since the conventional optical disk recording/reproducing apparatus cannot correctly measure a power of a main beam that is a part of the laser light outputted from an objective lens and is focused on a recording layer to contribute to recording/reproducing, it is difficult to accurately control a read power. A ratio of a proper read power to a threshold power of erasing is acquired beforehand. The read power is determined by measuring the threshold power of erasing and multiplying it by the ratio when learning of the read power is performed for each drive device. According to the read power learning method of this invention, it becomes possible to determine the proper read power regardless of performance variance of an optical pickup and sensitivity dispersion of a medium.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 21, 2012
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventors: Takahiro Kurokawa, Hiroyuki Minemura
  • Patent number: 8107339
    Abstract: A highly efficient and reliable reproduced signal evaluation method and an optical disc drive using that method in which assuming that the number of 2T's appearing successively in a predetermined evaluation bitstream is i, the evaluation bitstream is divided into a main bitstream (5+2i) long and sub bitstreams at the ends of the main bitstream. The check process to determine whether a predetermined evaluation bitstream is included in the binarized bitstreams is replaced with a main bitstream agreement check. This can prevent an increase in the circuit size. At the same time, by separately summing up for each main bitstream the calculated results of Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bitstream, the size of an evaluation summing circuit can be reduced.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: January 31, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Hiroyuki Minemura, Soichiro Eto, Takahiro Kurokawa, Shuichi Kusaba
  • Patent number: 8102750
    Abstract: When a super resolution technology for optical disks is used in a situation where optical disk management information is formed with a signal that cannot be reproduced by a reproduction method based on a conventional optical disk technology, optical disk drives cannot make recording adjustments and/or reproduction adjustments. An optical disk drive uses an optical disk that forms a management information signal with pits not smaller in size than optical resolution and can be read by a reproduction method based on a conventional optical disk technology. When the optical disk drive records information onto or reproduces information from the optical disk having the super resolution region, it is possible to make proper recording adjustments or reproduction adjustments and perform a proper recording operation or reproducing operation in an optical disk's information region for user information recording or reproduction.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: January 24, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd
    Inventors: Soichiro Eto, Toshimichi Shintani, Hiroyuki Minemura
  • Patent number: 8095844
    Abstract: An optical disc using super-resolution effects that achieves higher-density recording exceeding the optical resolution suffers from the signal-quality degradation caused by the normal resolution component included in the reproduction signal. To address this problem, a data reproduction method is provided. In the method, characteristic error patterns are identified and parity check codes in conformity with run-length limited coding are used to carry out efficient and reliable error correction. Error patterns caused by the normal resolution crosstalk are localized in the leading edges of a mark following a long space and in the trailing edges of a long mark. Whether an error exists in the data is determined by use of the parity check codes. When an error occurs, a pattern in which an error is most likely to occur is selected from the above-mentioned patterns by taking account of the edge shift direction, and then the error therein is corrected.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: January 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Minemura, Toshimichi Shintani, Yumiko Anzai, Soichiro Eto
  • Patent number: 8094535
    Abstract: A write type optical disk device with the PRML mode allows accuracy in the trial writing to be improved accompanied with the high speed processing while assuring the readout compatibility. A readout signal that has been A/D converted at timing that interposes the edge has its phase compensated with the even numbered FIR filter. The level at the edge point and the absolute values thereof are accumulated respectively so as to provide a circuit for detecting the edge shift and jitter. Coping with the high speed processing, the edge shift of the readout signal is detected at the position where the edge shift is around zero, thus improving the accuracy in learning of trial writing.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: January 10, 2012
    Assignees: Hitachi, Ltd, Hitachi-LG Data Storage, Inc.
    Inventor: Hiroyuki Minemura
  • Publication number: 20120002526
    Abstract: A highly efficient and reliable reproduced signal evaluation method and an optical disc drive using that method in which assuming that the number of 2T's appearing successively in a predetermined evaluation bitstream is i, the evaluation bitstream is divided into a main bitstream (5+2i) long and sub bitstreams at the ends of the main bitstream. The check process to determine whether a predetermined evaluation bitstream is included in the binarized bitstreams is replaced with a main bitstream agreement check. This can prevent an increase in the circuit size. At the same time, by separately summing up for each main bitstream the calculated results of Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bitstream, the size of an evaluation summing circuit can be reduced.
    Type: Application
    Filed: August 16, 2011
    Publication date: January 5, 2012
    Inventors: Hiroyuki Minemura, Soichiro Eto, Takahiro Kurokawa, Shuichi Kusaba