Patents by Inventor Hiroyuki Motozuka

Hiroyuki Motozuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150244546
    Abstract: An equalization method includes carrying out frequency domain conversion of M received signals into a 2M received vector having 2M elements, carrying out channel estimation and noise/interference estimation based on the 2M vector, calculating a 2M channel vector and a (2M)×(2M) noise/interference matrix, selecting a 2M?1 or less channel vector from the calculated 2M channel vector, selecting a (2M?1)×(2M?1) or less noise/interference matrix from the calculated (2M)×(2M) noise/interference matrix, calculating a 2M?1 or less equalization coefficient vector as equalization coefficients based on the selected 2M?1 channel vector and the selected (2M?1)×(2M?1) noise/interference matrix, selecting a 2M?1 or less received vector from the 2M received vector, and equalizing the selected 2M?1 received vector by using the calculated equalization coefficients.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 27, 2015
    Inventors: YOSHINORI SHIRAKAWA, NAGANORI SHIRAKATA, KOICHIRO TANAKA, HIROYUKI MOTOZUKA
  • Publication number: 20150244475
    Abstract: A radio communication apparatus includes a discrete Fourier transformer that performs a frequency-domain transform on each of a plurality of reception signals received at a plurality of receiver chains and generates a plurality of frequency-domain signals, a covariance matrix calculator that calculates covariance of the plurality of frequency-domain signals, a deviation calculator that calculates a cumulative value of covariance in a first frequency range and a second frequency range and calculates deviation of the covariance in the plurality of frequency ranges, and an adjacent-channel interference determiner that determines presence or absence of adjacent-channel interference using the cumulative value of the covariance.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 27, 2015
    Inventors: HIROYUKI MOTOZUKA, NAGANORI SHIRAKATA
  • Publication number: 20150244478
    Abstract: A radio communication device includes: a directivity control unit that configures each of directivities of a plurality of antennas; a directivity switching unit that switches between the directivities of the antennas; a reception quality estimation unit that measures a reception quality of a received signal received by the antennas; and a block error estimation unit that estimates a block error in reception data which is obtained by decoding the received signal. In the case where a block error occurs continuously for a predetermined number of times or longer and an amount of decrease in the reception quality is lower than a predetermined value, the directivity control unit re-adjusts a directivity to decrease the block error, based on a result of the estimation of the block error and a result of the measurement of the reception quality, the re-adjusted directivity being one of the directivities of the antennas.
    Type: Application
    Filed: February 20, 2015
    Publication date: August 27, 2015
    Inventors: NAGANORI SHIRAKATA, HIROYUKI MOTOZUKA
  • Publication number: 20150244071
    Abstract: A wireless communication device includes a directivity control unit that sets a directivity for a plurality of antennas, a directivity switching unit that switches the directivity for the plurality of antennas, and a reception quality estimation unit that measures the reception quality of a received signal received by the plurality of antennas. The directivity control unit uses the reception quality of a received signal directed to another station among the received signals to set the directivity in a direction in which an influence of interference from the other station is reduced.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 27, 2015
    Inventors: NAGANORI SHIRAKATA, HIROYUKI MOTOZUKA
  • Patent number: 9112743
    Abstract: An equalization method includes carrying out frequency domain conversion of M received signals into a 2M received vector having 2M elements, carrying out channel estimation and noise/interference estimation based on the 2M vector, calculating a 2M channel vector and a (2M)×(2M) noise/interference matrix, selecting a 2M?1 or less channel vector from the calculated 2M channel vector, selecting a (2M?1)×(2M?1) or less noise/interference matrix from the calculated (2M)×(2M) noise/interference matrix, calculating a 2M?1 or less equalization coefficient vector as equalization coefficients based on the selected 2M?1 channel vector and the selected (2M?1)×(2M?1) noise/interference matrix, selecting a 2M?1 or less received vector from the 2M received vector, and equalizing the selected 2M?1 received vector by using the calculated. equalization coefficients.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 18, 2015
    Assignee: Panasonic Corporation
    Inventors: Yoshinori Shirakawa, Naganori Shirakata, Koichiro Tanaka, Hiroyuki Motozuka
  • Publication number: 20150229330
    Abstract: A variable shifter includes: a plurality of shifters that cyclically shift input data having a plurality of bits or cyclically shifted data; and a control unit that selects a shift amount for each of the plurality of shifters in accordance with a predetermined cyclic shift amount. The number of types of the predetermined cyclic shift amount is smaller than the number of bits in the input data, each shifter selects one of a plurality of shift amounts in accordance with the predetermined cyclic shift amount, and the plurality of shift amounts have a combination of shift amounts that differ from one shifter to another.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 13, 2015
    Inventors: HIROYUKI MOTOZUKA, HIROYUKI YOSHIKAWA
  • Publication number: 20150222373
    Abstract: A receiving device that receives a signal in a receiving antenna. The receiving device includes a gain controller that adjusts a gain in the receiving device in response to information related to power of the signal, and a signal detector that determines whether, within a predetermined period after the information related to the power of the signal exceeds a first threshold value, the information related to the power of the signal exceeds a second threshold value which is larger than the first threshold value. The gain controller adjusts a search range of the gain in the receiving device based on a determination result of the signal detector with respect to the information related to the power of the signal.
    Type: Application
    Filed: January 27, 2015
    Publication date: August 6, 2015
    Inventors: KOICHIRO TANAKA, HIROYUKI MOTOZUKA, NAOYA YOSOKU
  • Patent number: 9065525
    Abstract: A receiving apparatus receives a signal via a receiving antenna and quantizes the signal. The receiving apparatus includes: a gain control section that adjusts gain in the receiving apparatus in accordance with electric power of the quantized signal; an electric power estimating section that estimates electric power of the signal before quantization of the signal received by the receiving antenna on the basis of the electric power of the quantized signal and the gain in the receiving apparatus; and an error detecting section that detects a reception error in a predetermined region of the quantized signal, and the gain control section adjusts a search range for the gain on the basis of a result of detection of the reception error in the predetermined region of the quantized signal and an electric power estimated value of the signal before quantization of the signal received by the receiving antenna.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 23, 2015
    Assignee: Panasonic Corporation
    Inventors: Naoya Yosoku, Koichiro Tanaka, Hiroyuki Motozuka
  • Patent number: 8700971
    Abstract: A parallel residue arithmetic operation unit is provided to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit includes input terminals to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units for calculating logical multiplications of part CRC values, and a cumulative adding unit for cumulatively adding values output from the AND units.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Motozuka
  • Publication number: 20140082455
    Abstract: A decoding device has a decoding section that has a plurality of decoding cores which decode a received packet (e.g., likelihoods generated as a result of demodulation), which will become data to be decoded, in parallel on a per-likelihood basis and in which a first decoding core and a second decoding core of a plurality of decoding cores can perform decoding in parallel and a control section that controls decoding, wherein the decoding section lets the second decoding core decode a second likelihood when the second likelihood is input in the middle of the first decoding core decoding the first likelihood of the data to be decoded, whereby another likelihood can be decoded by use of another decoding core in the middle of decoding of a certain likelihood. Thus, entire decoding speed is increased.
    Type: Application
    Filed: March 5, 2013
    Publication date: March 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Naoya Yosoku, Hiroyuki Yoshikawa, Hiroyuki Motozuka
  • Patent number: 8261163
    Abstract: A soft output decoder that receives code words corresponding to information words is provided. The soft output decoder calculates soft decision decoding results of the information words from likelihood values corresponding to candidate values adopted by the information words. The soft output decoder includes a hard decision decoder that decides one of the candidate values as an estimated value. The soft output decoder further includes a likelihood calculator that bans calculation of a likelihood value corresponding to the estimated value and that calculates other likelihood values corresponding to other candidate values in the likelihood values.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: September 4, 2012
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Motozuka
  • Publication number: 20100205518
    Abstract: In order to allow early stopping of codeblock decoding iterations, a cyclic redundancy check (CRC) is attached to each codeblock segment that pertains to the same transport block carrying information bits. The CRC for segment k is calculated for all bits within segments 1 to k. This allows also identifying cases of wrongly assumed CRC check results for segments 1 to k when the CRC attached to segment k+1 is evaluated.
    Type: Application
    Filed: August 18, 2008
    Publication date: August 12, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Alexander Golitschek Edler von Elbwart, Hiroyuki Motozuka
  • Publication number: 20100198892
    Abstract: A parallel residue arithmetic operation unit is provided to make it possible to reduce processing delay, and to make an additional multiplier or a residue arithmetic circuit unnecessary, so that a circuit can become small in size. In the parallel residue arithmetic operation unit, a parallel CRC calculation circuit (100) is comprised of input terminals (101)-(104) to which input data are divided into a plurality of sub-blocks and the sub-blocks are input in parallel, an initial value generating unit (110) for generating a part CRC corresponding to the forefront of each sub-block as an initial value, a part CRC generating unit (111)-(114) for receiving the part CRC corresponding to the forefront of each sub-block as the initial value and sequentially generating a residue part CRC in accordance with a recurrent equation, AND units (121)-(124) for calculating logical multiplications of part CRC values, and a cumulative adding unit (130) for cumulatively adding values output from the AND units (121)-(124).
    Type: Application
    Filed: August 21, 2007
    Publication date: August 5, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Hiroyuki Motozuka
  • Publication number: 20100169745
    Abstract: A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder (100) comprises a &ggr;? calculating section (101), timing adjusters (102, 103), a &ggr;? calculation section (104), and a &Lgr; calculating unit (110). The &Lgr; calculating unit (110) is composed of a hard decision decoding section (111), a loss likelihood calculating section (112), a win likelihood storage section (113), and a subtractor (114). The likelihoods determined by a Max-log-MAP decoder are separated into win likelihoods and loss likelihoods, and only the loss likelihoods are calculated. A hard decision decoding section (111) for sequentially specifying the states through which the maximum likelihood path passes is used for a method for distinguishing the win and loss likelihoods.
    Type: Application
    Filed: August 21, 2007
    Publication date: July 1, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Hiroyuki MOTOZUKA
  • Publication number: 20070067379
    Abstract: A reconfigurable data processing apparatus. In this apparatus, many cells A 100 for performing ALU processing and cells B 150 for performing bit processing are arranged, each cell includes n-bit input/output ports and the cells are connected through a network with n-bit buses. Furthermore, when the number of output bits is smaller than n, cell B 150 fixes bits of orders irrelevant to outputs to “0” or “1.” When the bussed ALU processing part and bit processing part are combined to perform data processing, this makes it possible to execute ALU processing and bit processing efficiently and realize high-speed, parallel processing.
    Type: Application
    Filed: October 6, 2004
    Publication date: March 22, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRAIL CO., LTD.
    Inventors: Hiroyuki Motozuka, Ryutaro Yamanaka
  • Publication number: 20070033153
    Abstract: A disaster prediction system that provides a plurality of mobile communications apparatuses with a function for detecting abnormal signals that are effective in natural disaster prediction, manages location information for the mobile communications apparatuses and appropriately sets areas of natural disaster prediction, collects a plurality of abnormality detection signals from the mobile communications apparatuses, analyzes these signals per area of prediction, improves the accuracy of natural disaster occurrence prediction, and transmits natural disaster-related information to a plurality of mobile communications apparatuses present in the areas of prediction.
    Type: Application
    Filed: October 25, 2004
    Publication date: February 8, 2007
    Inventors: Ryutaro Yamanaka, Hiroyuki Motozuka, Mitsuru Uesugi
  • Publication number: 20070005346
    Abstract: A mobile terminal apparatus that considers intervals between key input operations when characters are input, and, when there is an interval grater than a certain period of time between operations, or when a shift is made to different character input, reads aloud the voice corresponding to the stored input character and reads aloud only the character the user needs to check. In this apparatus, when other characters are continuously input by the same key input within a predetermined time, character selection fixing section 201 updates the stored content in present candidate storage section 202, outputs the updated candidate character to display control section 204 as a displaying character and displays the updated candidate character on liquid crystal display section 103. At this time, the voice corresponding to the displaying candidate character is not reproduced.
    Type: Application
    Filed: October 25, 2004
    Publication date: January 4, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinji Ueda, Hiroyuki Motozuka, Tomohiro Imai