Abstract: For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode.

Abstract: An image forming apparatus is provided in which an electrostatic latent image formed on a surface of a photoreceptor is developed into a toner image with a developing device, and in which a printing paper transported on a transport belt is brought into contact with the surface of the photoreceptor and an electric field is applied to the printing paper from a rear surface of the transport belt by a transfer roller so as to transfer the toner image onto the printing paper, the transfer roller capable of applying different levels of electric field to the printing paper, so that a predetermined transfer electric field is applied to a region other than a leading edge of the printing paper being transported, and that a weak electric field weaker than the predetermined transfer electric field is applied to the leading edge of the printing paper being transported.

Abstract: A sheet conveying device that facilitates solution of a jam of a sheet and which is capable of inhibiting shortening of life due to a jam is provided. A sheet having a bent leading end that is very likely to jam is positively made to jam at a blocking portion formed on an upstream side of an image forming station in a sheet conveying direction thereof. Consequently, it is possible to more easily perform an operation of solving a jam than in a case where a jam of the sheet occurs in the image forming station. Moreover, it is possible to prevent deterioration of the image forming station due to a jam, and inhibit shortening of the life of the image forming station resulting from a jam.

Abstract: A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.

Abstract: A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.

Abstract: An image recording apparatus includes a first pullout unit, a second pullout unit, and a first lock mechanism. The first unit is movable along a first axis between a first retracted position where the first unit is fully retracted in the apparatus, and a first exposed position where at least one side surface thereof is fully exposed to the front of the apparatus. The second unit is movable along a second axis, which is perpendicular to the first axis, between a second retracted position where the second unit is fully retracted in the first unit, and a second exposed position where the second unit is exposed to a side of the side surface of the first unit. The first lock mechanism prevents movement of the second unit from the second retracted position to the second exposed position when the first unit is not in the first exposed position.

Abstract: A transfer mechanism includes: a transfer unit having a transfer belt; and a belt contact and separation assembly for bringing the transfer belt into, and separating it away from, an electrostatic latent image support by shifting the position of the transfer unit. The belt contact and separation assembly includes:a multiple number of transfer unit shifters that abut the transfer unit and shift the position of the transfer unit; a multiple number of linkage members that link with the plural transfer unit shifters, correspondingly; an elastic member for coupling the plural linkage members; and a driver for actuating the transfer unit shifters through the linkage members.

Abstract: A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.

Abstract: A charging device includes a long electrode, a cleaning member, a timing device, a drive source, a load measuring device, and a control device. The drive source moves the cleaning member in the outward direction for a first time period after the outward passage time and then reverses the cleaning member in the homeward position. The load measuring device measures driving load imposed on the drive source while the cleaning member is being moved. The control device controls motion of the drive source to turn the cleaning member from the outward direction to the homeward direction at a predetermined objective point near the second end, based on sum of driving loads imposed on the drive source while the cleaning member is being moved from the first point to a second point located along the outward direction.

Abstract: In an image forming method, an electrostatic latent image formed on a surface of a photoreceptor is developed into a developer image with a developer, and a printing paper transported on a transfer belt is brought into contact with the surface of the photoreceptor so as to transfer the developer image onto the printing paper. The printing paper is transported in a proper transport direction, in which a projection generated in one direction on the printing paper as a result of cutting the printing paper in a printing paper manufacturing process does not face a surface of the transfer belt at a leading edge of the printing paper being transported on the transfer belt. In this way, even in the presence of the projection generated when the printing paper is cut, the printing paper naturally strips off from the surface of the photoreceptor, thereby preventing toner contamination caused by a striping claw in contact with the leading edge of the printing paper.

Abstract: A charging device includes a rotatable screw gear, a motor, a support, and a protruding member. The screw gear is positioned along length of a linear electrode. The motor rotates the screw gear in forward and reverse directions. The support holds the cleaning member mounted so as to be in contact with the electrode, and is mounted unrotatably but reciprocably between a first end and a second end of the electrode. The member extends perpendicular to the length of the electrode from the support, and has a projection for being elastically fitted into a thread groove of the screw gear along a radial direction of the screw gear. The member is configured in such a manner that a distance between a starting point of elastic deformation of the member and a contact point between the projection and a thread of the screw gear differs according to whether the support is moved forward or backward.

Abstract: In a partial display mode, a source IC outputs a start signal at an “H” level designating the start of vertical scanning by a vertical scanning circuit, over a plurality of cycles from before a time T1 to after a time T8. A plurality of shift registers sequentially shift the start signal in synchronization with a clock signal to sequentially drive a plurality of activation enable signals, respectively, to an “H” level. Then, after time T8 when first to fourth activation enable signals simultaneously attain an “H” level, the source IC outputs an enabling signal at an “H” level to the vertical scanning circuit. In response, the vertical scanning circuit simultaneously activates first to fourth gate lines corresponding to the first to the fourth activation enable signals, respectively.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: An image transfer device includes an image transfer electrode roller which is disposed face to face with a photosensitive drum with a printing sheet passing between the image transfer electrode roller and the photosensitive drum. The image transfer device is structured such that the image transfer electrode roller can be shifted back and forth along a transport direction of the printing sheet. A voltage is applied to the image transfer electrode roller to create an image transfer electric field between the image transfer electrode roller and the photosensitive drum for transferring a toner image formed on the photosensitive drum onto the printing sheet. The image transfer electrode roller is brought to one of different positions along a transport direction of the printing sheet selected according to information on properties of the printing sheet and transfers the toner image onto the printing sheet at that position.

Abstract: Transfer roller(s) is/are such that either end thereof is formed from fibrous electrically conductive component(s) and such that cylindrical portion(s) in central region(s) is/are, for example, formed from metal roller-like structure(s), either fibrous electrically conductive component outer end being arranged so as to extend somewhat beyond either transfer/transport belt side. Furthermore, outside diameter(s) approximated by tips of respective individual fiber(s) of fibrous electrically conductive component(s) is/are somewhat larger than diameter(s) of metal roller-like structure(s). This makes it possible for electric field(s) to be applied, and for charging to occur, along the full width(s) of transfer/transport belt(s).

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.

Abstract: A shift register circuit comprises a first transistor between a gate line output terminal and a clock terminal, a second transistor between the gate line output terminal and a first power supply terminal, a third transistor between a carry signal output terminal and the clock terminal and a fourth transistor between the carry signal output terminal and the first power supply terminal. Gates of the second and fourth transistors are connected to each other. A fifth transistor connected between a gate of the first transistor and a second power supply terminal and a sixth transistor connected between a gate of the third transistor and the second power supply terminal have gates both of which are connected to an input terminal. With this constitution, it is possible to suppress an influence between two synchronous output signals outputted from the shift register circuit.