Patents by Inventor Hiroyuki Nakahira
Hiroyuki Nakahira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7215623Abstract: An analog filter is placed at a stage previous to an analog-digital converter (ADC), and a waveform equalizer is placed at a stage subsequent to the ADC. The sampling frequency of the ADC is determined by a clock generation section according to the relationship between the bit rate of an input reproduction signal and the characteristic of the analog filter. The number of taps is changed according to the relationship between the bit rate of the input reproduction signal and the characteristic of the analog filter. Further, the tap coefficients of a waveform equalizer are changed according to the height of the frequency band of the input reproduction signal. A waveform evaluation section generates a signal that evaluates a waveform equalization signal transmitted from the waveform equalizer to a Viterbi decoder, whereby adaptive waveform equalization is realized.Type: GrantFiled: November 12, 2003Date of Patent: May 8, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Nakahira, Takashi Morie
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Publication number: 20070082908Abstract: A compound represented by the following formula (I), a prodrug thereof, or a pharmaceutically acceptable salt of either. These are compounds having high DPP-IV inhibitory activity and improved in safety, nontoxicity, etc. (I) [In the formula, R1 represents hydrogen, optionally substituted alkyl, etc.; the solid line and dotted line between A1 and A2 indicate a double bond (A1=A2), etc.; A1 represents a group represented by the formula C(R2), etc.; A2 represents a group represented by the formula C(R4), etc.; R2 represents hydrogen, optionally substituted alkyl, etc.; R4 represents hydrogen, optionally substituted alkyl, etc.; R6 represents hydrogen, optionally substituted aryl, etc.; and —Y represents, e.g.; a group represented by the formula (A): (A) (wherein m1 is 0, 1, 2, or 3; and R7 is absent, or one or two R7's are present and each independently represents optionally substituted alkyl, etc.).Type: ApplicationFiled: August 25, 2004Publication date: April 12, 2007Applicant: DAINIPPON SUMITOMO PHARMA CO., LTD.Inventors: Hiroyuki Nakahira, Hitoshi Hochigai, Tatsuya Takeda, Tomonori Kobayashi, William Hume
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Patent number: 7068584Abstract: The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value.Type: GrantFiled: March 3, 2003Date of Patent: June 27, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Hiroyuki Nakahira, Akira Yamamoto
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Publication number: 20050270677Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.Type: ApplicationFiled: August 8, 2005Publication date: December 8, 2005Inventors: Hirokuni Fujivama, Shiro Dosho, Hiroyuki Nakahira, Akira Yamamoto, Hiroki Mouri
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Patent number: 6970313Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.Type: GrantFiled: March 30, 2000Date of Patent: November 29, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokuni Fujiyama, Shiro Dosho, Hiroyuki Nakahira, Akira Yamamoto, Hiroki Mouri
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Publication number: 20050219985Abstract: As shown in FIG. 1, in the reproduced signal processing apparatus (100) of the present invention, the pattern predictor (103) predicts a predicted value which is a data sequence of a reproduced signal X and judges whether the predicted value matches a previously set specific pattern or not, and the adaptive equalizer (110) performs adaptive equalization on the reproduced signal X with timely updating the coefficients W of the digital filter according to the judgement result from the pattern predictor (103), and the selection circuit (104) outputs one of the output from the adaptive equalizer (110) and the predicted value as a waveform-equalized output Y on the basis of the judgement result. The reproduced signal processing apparatus (100) so constructed can realize optimal waveform equalization for coping with the non-linear distortion included in the reproduced signal.Type: ApplicationFiled: September 2, 2003Publication date: October 6, 2005Inventor: Hiroyuki Nakahira
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Publication number: 20040165510Abstract: An analog filter is placed at a stage previous to an analog-digital converter (ADC), and a waveform equalizer is placed at a stage subsequent to the ADC. The sampling frequency of the ADC is determined by a clock generation section according to the relationship between the bit rate of an input reproduction signal and the characteristic of the analog filter. The number of taps is changed according to the relationship between the bit rate of the input reproduction signal and the characteristic of the analog filter. Further, the tap coefficients of a waveform equalizer are changed according to the height of the frequency band of the input reproduction signal. A waveform evaluation section generates a signal that evaluates a waveform equalization signal transmitted from the waveform equalizer to a Viterbi decoder, whereby adaptive waveform equalization is realized.Type: ApplicationFiled: November 12, 2003Publication date: August 26, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroyuki Nakahira, Takashi Morie
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Patent number: 6778483Abstract: An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word (8B) and the ternary code word (5T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.Type: GrantFiled: October 31, 2001Date of Patent: August 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Takashi Yamamoto, Hiroyuki Nakahira, Akira Yamamoto
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Patent number: 6745218Abstract: An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.Type: GrantFiled: March 16, 2000Date of Patent: June 1, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Hiroyuki Nakahira, Hirokuni Fujiyama, Hiroki Mouri
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Patent number: 6684378Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: GrantFiled: November 5, 2001Date of Patent: January 27, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Publication number: 20030198165Abstract: The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value.Type: ApplicationFiled: March 3, 2003Publication date: October 23, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroki Mouri, Hiroyuki Nakahira, Akira Yamamoto
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Publication number: 20030185291Abstract: The present invention provides an equalizer capable of accurately compensating for non-linearity of an input signal due to the asymmetry phenomenon, etc., during the disk production process. Two tap coefficients are provided in a coefficient unit. A comparator compares the value of a middle tap signal, which is a reference signal, and a threshold, so as to produce a selection signal based on the comparison result. The coefficient unit selects one of the two tap coefficients as the selected tap coefficient based on the selection signal, and a tap signal is multiplied with the selected tap coefficient. Thus, it is possible to adaptively switch the tap coefficients of the equalizer as a whole based on the value of the middle tap signal, which is the reference signal. Therefore, it is possible to accurately compensate for the non-linearity of the input signal.Type: ApplicationFiled: March 10, 2003Publication date: October 2, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroyuki Nakahira, Koichi Nagano, Koji Okamoto, Akira Yamamoto
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Patent number: 6460168Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: GrantFiled: March 27, 2000Date of Patent: October 1, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Patent number: 6424184Abstract: A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.Type: GrantFiled: March 24, 1999Date of Patent: July 23, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shiro Sakiyama, Hiroyuki Nakahira, Masaru Fukuda, Akira Matsuzawa, Shiro Dosho, Shinichi Yamamoto
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Publication number: 20020054557Abstract: An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word (8B) and the ternary code word (5T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.Type: ApplicationFiled: October 31, 2001Publication date: May 9, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Takashi Yamamoto, Hiroyuki Nakahira, Akira Yamamoto
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Publication number: 20020042902Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: ApplicationFiled: November 5, 2001Publication date: April 11, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Patent number: 6067536Abstract: A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity.Type: GrantFiled: May 29, 1997Date of Patent: May 23, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masakatsu Maruyama, Hiroyuki Nakahira, Masaru Fukuda, Shiro Sakiyama
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Patent number: 5636327Abstract: In a multilayered neural network for recognizing and processing characteristic data of images and the like by carrying out network arithmetical operations, characteristic data memories store the characteristic data of the layers. Coefficient memories store respective coupling coefficients of the layers other than the last layer. A weight memory stores weights of neurons of the last layer. Address converters carry out arithmetical operations to find out addresses of nets of the network whose coupling coefficients are significant. A table memory outputs a total coupling coefficient obtained by inter-multiplying the significant coupling coefficients read out from the coefficient memories of the layers. A cumulative operation unit performs cumulative additions of the product of the total coupling coefficient times the weight of the weight memory. Arithmetical operations are carried out only on particular nets with a significant coupling coefficient value. The speed of operation and recognition can be improved.Type: GrantFiled: March 23, 1995Date of Patent: June 3, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Nakahira, Shiro Sakiyama, Masakatsu Maruyama, Susumu Maruno
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Patent number: 5621862Abstract: In an information processing apparatus for implementing a neural network, if an input vector is inputted to a calculating unit, a neuron which responds to the input vector is retrieved in accordance with network interconnection information stored in a first storage unit and the neuron number indicating the retrieved neuron is written in a first register. The calculating unit reads out the internal information of the neuron stored in a second storage unit by using the neuron number, writes it in a second register, and calculates the sum of products of the outputs of the neurons and the connection loads of synapses connected to the neurons. By repeating the sequence of operations by the number of times corresponding to the total number of input vectors, a recognition process is executed. The neural network can easily be expanded by rewriting the contents of the first and second storage units.Type: GrantFiled: July 28, 1994Date of Patent: April 15, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Nakahira, Masakatsu Maruyama, Shiro Sakiyama, Susumu Maruno, Toshiyuki Kouda, Masaru Fukuda
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Patent number: 5550544Abstract: The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.Type: GrantFiled: February 23, 1994Date of Patent: August 27, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Sakiyama, Shiro Dosho, Masakatsu Maruyama, Hiroyuki Nakahira, Toshiyuki Shono, Akira Matsuzawa