Abstract: An object detection device subjects fixed-length data having a decimal point position set therein to an arithmetic processing corresponding to respective layers in a plurality of layers configuring a multilayer neural network to which an input image is input, the arithmetic processing being performed in accordance with a processing algorithm for the multilayer neural network to which an input image is input. In the arithmetic processing, the object detection device counts the upper limit number of saturations, which is a number of times that upper limit value of a value range determined by the decimal point position is exceeded, and the lower limit number of saturations, which is a number of times that the lower limit value of the value range is not reached.

Abstract: An embodiment is a packet capture device including a first local timer synchronized with an external global timer, a second local timer, a time stamp assign unit for assigning a time stamp to a inputted packet signal based on the second local timer, a filter unit for selecting the packet signal to which the time stamp is assigned, a capture file generation unit for receiving the selected packet signal, and a storage unit for storing a capture file generated in the capture file generation unit, wherein the capture file generation unit calculate a difference between a timer value of the first local timer and a timer value of the second local timer to correct the time stamp value on the basis of the difference.

Abstract: Composition including (a) a fluoropolymer; and (b1) at least one of a compound represented by the formula (4) ((H—(CF2)7—COO)pM1) or the formula (4?) ((H—(CF2)8—COO)pM1) of the present disclosure, both respectively in an amount of 100 ppb or less relative to the fluoropolymer, or (b2) at least one of a compound represented by the formula (5) ((H—(CF2)13—COO)pM1) or the formula (5?) ((H—(CF2)14—COO)pM1) of the present disclose, both respectively in an amount of 100 ppb or less relative to the fluoropolymer.

Abstract: A charging system includes a power transfer device and a rapid charging battery. The power transfer device includes a first power transfer unit being compatible with a first charging standard specifying that the rapid charging battery is to be charged at a predetermined current value. The rapid charging battery includes a first charging unit being compatible with the first charging standard, and a second power transfer unit being compatible with a second charging standard specifying that power is to be transferred at a predetermined current value that is lower than the predetermined current value specified by the first charging standard.

Abstract: An object detecting device includes: an overall processing unit configured to perform object detection processing on an input image; an allocation processing unit configured to determine a segmented image for each frame which is subject to object detection among the plurality of segmented images in advance in a cycle of N frames, and reserve the determined segmented image; a selection processing unit configured to select and output, for each frame, some of the segmented images that are subject to object detection among the plurality of segmented images based on a reservation result from the allocation processing unit; a division processing unit configured to perform object detection processing on each of the segmented images output from the selection processing unit; and a synthesizing processing unit configured to synthesize an object detection result from the overall processing unit and an object detection result from the division processing unit.

Abstract: A packet capture device a packet analysis unit that analyzes an input packet; a flow identification unit that identifies a flow as a capture target; an output adjustment unit that adjusts a packet amount of the flow as the capture target to be output to a storage unit; a buffer unit that temporarily accumulates a packet of the flow as the capture target; and the storage unit that stores the packet of the flow as the capture target, in which the output adjustment unit is configured to decide whether to output the packet of the flow as the capture target to the storage unit for each predetermined measurement interval on the basis of a measurement result of the packet amount of the capture target in a predetermined measurement interval, and discard the packet not to be output to the storage unit.

Abstract: When an output feature map to be an output of convolution processing is output, the output feature map is output to a storage unit for each of divided small regions. When each small region is output to the storage unit, in a case where a feature included in the small region is the same as a predetermined feature or a feature of a small region output in the past, the predetermined feature or the feature of a small region output in the past is compressed and output to the storage unit.

Abstract: A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.

Abstract: A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.

Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

Abstract: A liquid crystal display device includes a plurality of video signal lines that extends in columns in a display area, a plurality of inversion control signal line each supplied with an inversion control signal for controlling inversion, a first selector that selects one of a pair of amplifiers different in the polarity from each other to input signals corresponding to a pair of adjacent video signal lines on the basis of the inversion control signal, and a second selector that selects one of a pair of the corresponding adjacent video signal lines to input signals output from the pair of amplifiers on the basis of the inversion control signal, in which at least one of the signals to be supplied to the plurality of inversion control signal lines is a signal different from other signals.

Abstract: A nonvolatile semiconductor memory device includes first and second memory blocks which are disposed adjacent to each other in a first direction. The first and second memory blocks each include a plurality of bit lines, a plurality of word lines, which are disposed to extend in a second direction, and a memory cell, which is connected to any of the plurality of word lines. The first memory block includes a first selection gate line which is connected to one end of the memory cell, and the second memory block includes a second selection gate line in the same manner. An end portion of one end of the first selection gate line includes an L-shaped portion, and an end portion of one end of the second selection gate line includes a linear portion. A first contact is disposed on the L-shaped portion of the first selection gate.

Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor.

Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.

Abstract: A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: According to one embodiment, a resistance change memory includes a memory cell array area and a resistive element area on a substrate. A first memory cell array in the memory cell array area includes a first control line, a second control line above first control line, and a first cell unit between the first and second control lines. A second memory cell array on the first memory cell array includes the second control line, a third control line above the second control line, and a second cell unit between the second and the third control lines. And a resistive element in the resistive element area includes resistance lines, and a resistor connected to the resistance lines. The resistor includes the same member as one of a member of the cell unit and a member of a contact plug.