Abstract: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. Avoid part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto.

Abstract: According to one embodiment, a resistance change memory includes a memory cell array area and a resistive element area on a substrate. A first memory cell array in the memory cell array area includes a first control line, a second control line above first control line, and a first cell unit between the first and second control lines. A second memory cell array on the first memory cell array includes the second control line, a third control line above the second control line, and a second cell unit between the second and the third control lines. And a resistive element in the resistive element area includes resistance lines, and a resistor connected to the resistance lines. The resistor includes the same member as one of a member of the cell unit and a member of a contact plug.

Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.

Abstract: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto.

Abstract: According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.

Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.

Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

Abstract: A speed doubling circuit receiving display data in one frame period and outputting field A display data and field B display data in one frame period. A field conversion circuit converts the field A display data to have a highest gray-scale if the display data has a high gray-scale, and converts the field B display data to have a lowest gray-scale if the display data has a low gray-scale. Between the speed doubling circuit and field conversion circuit, an emphasis circuit is disposed which emphasizes each of the field A display data and field B display data in accordance with the display data one frame period before and the display data in the present frame period.

Abstract: A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conductivity are formed on the semiconductor substrate. The first contact plugs has a circular planar shape. The second contact plug has an elliptical planar shape and is formed on a source or a drain in one of the second MOS transistors. The first contact plugs are formed on sources or drains in the remaining second MOS transistors and the first MOS transistor.

Abstract: A matrix display device has first and second discharge sustaining electrode drive circuits that perform power recovery for the capacitance load through an LC resonance circuit using an inductor. During a luminescence emission period, a discharge is effected for display by applying an alternating voltage between each of plural first discharge sustaining electrodes and each of plural second discharge sustaining electrodes with a capacitance load corresponding to each display pixel. In the address scanning operation, the scan drive circuit selects the first discharge sustaining electrode per line, and in the discharge sustaining operation, the scan drive circuit provides a function for recovering power on the first discharge sustaining electrode. This is intended to decrease loss in the power recovery operation.

Abstract: A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in series between the two select transistors. A distance between the first electrodes and a distance between the first electrodes which is adjacent to the second electrodes and adjacent second electrodes are each at least double a distance between second electrodes. A surface of the substrate between second electrodes is flush with the surface of the substrate between the first electrode and the adjacent second electrodes. The surface of the substrate between the first electrodes is positioned lower than the surface of the substrate between the first electrodes and the second electrodes.

Abstract: The disclosed invention provides a display device for performing a gradation display, using a plurality of subframes of image into which one frame of image is divided, and a display method that reduces dynamic false contour noises occurring when the image is displayed and is suitable for plasma display panels and the like. Dynamic false contour noise reduction is performed by detecting luminance on/off state change (carry up/carry down) in a region where a smooth tone level change occurs and interchanging the tone values of pixels in the region. The reduction processing is controlled, based on an amount of motion of an original image and a display load ratio, so that dynamic false contour noise reduction is performed favorably. By carrying out different ways of processing for each frame, noise reduction in the time domain is performed.

Abstract: Scan electrode potential detected by a feedback switch is inputted into a negative-phase input terminal of an amplifier, reference selection potential from a reference-selection-potential-signal generation circuit is inputted into a positive-phase input terminal of the amplifier, and the reference-selection-potential-signal generation circuit delays reference potential of a reference voltage source, thereby scan electrode potential without overshooting components can be achieved.

Abstract: A display device includes a pixel array having a plurality of pixels, a plurality of first signal lines and a plurality of second signal lines. A first driving circuit outputs scanning signals to the plurality of first signal lines, and a second driving circuit outputs display signals to the plurality of second signal lines. Each pixel of the plurality of pixels is operated in a normally black-displaying mode, the first driving circuit repeats a first step of sequentially selecting N lines of the plurality of first signal lines and a second step of selecting Z lines of the plurality of first signal lines that are separate from the N lines, where N and Z are natural numbers, and the second driving circuit repeats outputting N times the display signals and outputting one time a blanking signal which masks an image displayed on corresponding pixels.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.

Abstract: A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.