Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.

Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

Abstract: A speed doubling circuit receiving display data in one frame period and outputting field A display data and field B display data in one frame period. A field conversion circuit converts the field A display data to have a highest gray-scale if the display data has a high gray-scale, and converts the field B display data to have a lowest gray-scale if the display data has a low gray-scale. Between the speed doubling circuit and field conversion circuit, an emphasis circuit is disposed which emphasizes each of the field A display data and field B display data in accordance with the display data one frame period before and the display data in the present frame period.

Abstract: A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conductivity are formed on the semiconductor substrate. The first contact plugs has a circular planar shape. The second contact plug has an elliptical planar shape and is formed on a source or a drain in one of the second MOS transistors. The first contact plugs are formed on sources or drains in the remaining second MOS transistors and the first MOS transistor.

Abstract: A matrix display device has first and second discharge sustaining electrode drive circuits that perform power recovery for the capacitance load through an LC resonance circuit using an inductor. During a luminescence emission period, a discharge is effected for display by applying an alternating voltage between each of plural first discharge sustaining electrodes and each of plural second discharge sustaining electrodes with a capacitance load corresponding to each display pixel. In the address scanning operation, the scan drive circuit selects the first discharge sustaining electrode per line, and in the discharge sustaining operation, the scan drive circuit provides a function for recovering power on the first discharge sustaining electrode. This is intended to decrease loss in the power recovery operation.

Abstract: A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in series between the two select transistors. A distance between the first electrodes and a distance between the first electrodes which is adjacent to the second electrodes and adjacent second electrodes are each at least double a distance between second electrodes. A surface of the substrate between second electrodes is flush with the surface of the substrate between the first electrode and the adjacent second electrodes. The surface of the substrate between the first electrodes is positioned lower than the surface of the substrate between the first electrodes and the second electrodes.

Abstract: The disclosed invention provides a display device for performing a gradation display, using a plurality of subframes of image into which one frame of image is divided, and a display method that reduces dynamic false contour noises occurring when the image is displayed and is suitable for plasma display panels and the like. Dynamic false contour noise reduction is performed by detecting luminance on/off state change (carry up/carry down) in a region where a smooth tone level change occurs and interchanging the tone values of pixels in the region. The reduction processing is controlled, based on an amount of motion of an original image and a display load ratio, so that dynamic false contour noise reduction is performed favorably. By carrying out different ways of processing for each frame, noise reduction in the time domain is performed.

Abstract: Scan electrode potential detected by a feedback switch is inputted into a negative-phase input terminal of an amplifier, reference selection potential from a reference-selection-potential-signal generation circuit is inputted into a positive-phase input terminal of the amplifier, and the reference-selection-potential-signal generation circuit delays reference potential of a reference voltage source, thereby scan electrode potential without overshooting components can be achieved.

Abstract: A display device includes a pixel array having a plurality of pixels, a plurality of first signal lines and a plurality of second signal lines. A first driving circuit outputs scanning signals to the plurality of first signal lines, and a second driving circuit outputs display signals to the plurality of second signal lines. Each pixel of the plurality of pixels is operated in a normally black-displaying mode, the first driving circuit repeats a first step of sequentially selecting N lines of the plurality of first signal lines and a second step of selecting Z lines of the plurality of first signal lines that are separate from the N lines, where N and Z are natural numbers, and the second driving circuit repeats outputting N times the display signals and outputting one time a blanking signal which masks an image displayed on corresponding pixels.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.

Abstract: The present invention is directed to reduce power consumption in a standby operation period as a period of holding display in a no-power state. An electronic paper display has an electronic paper display panel, a display driver/controller, a battery, and a booster power source circuit. The display panel can display data by writing display data and, after that, can hold the display in a no-power state. The booster power source circuit generates a boosted power source voltage by an operation of boosting power source voltage from the battery, and the display driver/controller executes the writing of the displayed data to the display panel by using the boosted power source voltage. In the following standby operation period in which the display panel holds the display in the no-power state, the boosting operation of the booster power source circuit is stopped.

Abstract: A liquid crystal driving device is provided, which can reduce the problem of contrast lowering of the liquid crystal display screen due to the decrease of the driving current of LED, by the control which is performed in order to cope with the decrease of the maximum rated current of LED as a light source of the backlight at a high temperature. The liquid crystal driving device includes a liquid crystal driving circuit, a backlight control unit, and display data expansion circuits. The liquid crystal driving circuit generates a liquid crystal driving signal to be supplied to a liquid crystal display panel in response to display data. The backlight control unit reduces driving current of the light emitting diode as a light source of the backlight module to illuminate the liquid crystal display panel, in response to the temperature rise of the liquid crystal display panel.

Abstract: In a plasma display apparatus and its drive circuit, a period that capacitance Cxa formed between an address electrode and an X-discharge maintaining electrode and capacitance Cya formed between the address electrode and a Y-discharge maintaining electrode are charged is provided when the address electrode is driven so that the address electrode is set to high-impedance state during a discharge maintaining period to reduce apparent capacitance. Furthermore, the charge period is set in a power withdrawing period and thereafter the address electrode is set to high-impedance state to change final arrival potential for power withdrawal to a discharge maintaining voltage.

Abstract: A one-frame interval is divided into a light field interval and a dark field interval. In the light field interval, the display data of high tones is displayed, while in the dark field interval, the display data of low tones is displayed. This divisional display makes it possible to pseudoly display the tones of the input display data. Then, in a case that the tones of the input display data is on the lower tone side, the display data of the dark field is set to the corresponding minimum tone with the minimum luminance, while in a case that the tone of the input display data is on the higher tone side, the display data of the light field is set to the corresponding maximum tone with the maximum luminance.

Abstract: A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.

Abstract: A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.