Patents by Inventor Hiroyuki Nitta

Hiroyuki Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7038651
    Abstract: In a hold-type display device, such as a liquid crystal display device, so-called blurring which appears on a profile of a displayed animated image can be suppressed without degrading the brightness of the image. An image based on video data to be inputted to a display device is displayed for every frame period and, thereafter, the image is masked with a blanking image. Here, the ratio between an image display period of the video data and a blanking image display period in one frame period is adjusted, based on the number of pixel rows selected in a pixel array in response to a scanning clock for respective periods, the frequency of the scanning clock, and shortening of a horizontal period of display signal inputting to every pixel row with respect to a horizontal scanning period of the video data, whereby the image can be efficiently cancelled using the blanking image.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: May 2, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Nitta, Tsutomu Furuhashi, Junichi Hirakata, Yoshinori Tanaka, Kazuyoshi Kawabe
  • Patent number: 7027018
    Abstract: A hold-type display device for eliminating blurring without damaging the display brightness of moving images. The display device includes a pixel array including a plurality of pixels, a plurality of first signal lines, a plurality of second signal lines, a first driving circuit outputting scanning signals to the plurality of first signal lines, and a second driving circuit outputting display signals to the plurality of second signal lines. The first driving circuit repeats a step for sequentially selecting the first signal lines every Y lines for every N times and a step for selecting the first signal lines every Z lines for every M times which follows the N times. The second driving circuit repeats outputting N times the display signals and outputting M times a blanking signal which masks an image displayed on corresponding pixels.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 11, 2006
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroyuki Nitta, Nobuyuki Koganezawa, Nobuhiro Takeda, Tsutomu Furuhashi, Masashi Nakamura
  • Patent number: 7006069
    Abstract: In a display device having a pixel array in which a plurality of pixels are arranged two-dimensionally along a first direction and a second direction, each of the pixels includes a pair of electrodes applying a voltage to liquid crystals, respective groups of the pixels arranged along the first direction form a plurality of pixel-rows juxtaposed along the second direction, and respective groups of the pixels arranged along the second direction form a plurality of pixel-columns juxtaposed along the first direction, the present invention repeats a first step for selecting every Y rows of the pixel-rows sequentially along the second direction N-times and applying an image signal to one of the pair of electrodes provided for each one of the pixels belonging to the each Y rows of the pixel-rows as selected, and a second step for selecting every Z rows of the pixel-rows sequentially along the second direction M-times and applying a blanking signal to the one of the pair of electrodes provided for each one of the pi
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: February 28, 2006
    Assignees: Hitachi Displays, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Masahiro Tanaka, Hiroyuki Nitta, Nobuhiro Takeda, Masashi Nakamura
  • Publication number: 20050206002
    Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
    Type: Application
    Filed: May 5, 2005
    Publication date: September 22, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nitta, Yoshiaki Fukuzumi, Yusuke Kohyama
  • Publication number: 20050168425
    Abstract: An active matrix type display device is driven by inverting polarities of gray scale voltages every nth rows of a pixel array of the display device where n?2. The first rows immediately after the inversion of polarities of the gray scale voltages in the respective columns of the pixel array is dispersed within the pixel array in terms of time and space.
    Type: Application
    Filed: December 15, 2004
    Publication date: August 4, 2005
    Inventors: Naoki Takada, Yoshihisa Ooishi, Hiroyuki Nitta
  • Publication number: 20050157578
    Abstract: A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
    Type: Application
    Filed: March 9, 2005
    Publication date: July 21, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuhiro Noguchi, Akira Goda, Hiroyuki Nitta
  • Patent number: 6906419
    Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nitta, Yoshiaki Fukuzumi, Yusuke Kohyama
  • Publication number: 20050101081
    Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.
    Type: Application
    Filed: September 8, 2004
    Publication date: May 12, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Goda, Hiroyuki Nitta
  • Publication number: 20050083353
    Abstract: A correction circuit produces correction data, which is used to shorten a response time in a display panel, using first display data received from an external device and second display data stored in a frame memory, and appends the correction data to the first display data. The correction circuit includes: a detection information production circuit that detects based on first color information, second color information, and third color information, which is inferred from the response characteristic of the display panel and represents a change of a gray-scale level from one level to other, whether a color gap is produced during the change of a gray-scale level from one level to other; and a production circuit that when the detection information production circuit detects that a color gap is produced during the change of a gray-scale level from one level to other, produces correction data for the purpose of preventing production of the color gap.
    Type: Application
    Filed: August 10, 2004
    Publication date: April 21, 2005
    Inventors: Junichi Maruyama, Hiroyuki Nitta
  • Patent number: 6882592
    Abstract: A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: April 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Noguchi, Akira Goda, Hiroyuki Nitta
  • Publication number: 20050024974
    Abstract: A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
    Type: Application
    Filed: October 30, 2003
    Publication date: February 3, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuhiro Noguchi, Akira Goda, Hiroyuki Nitta
  • Publication number: 20050023696
    Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
    Type: Application
    Filed: August 27, 2004
    Publication date: February 3, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nitta, Yoshiaki Fukuzumi, Yusuke Kohyama
  • Publication number: 20040263540
    Abstract: A display control circuit divides M display data for M pixels assigned to each of plural display driving circuits among display data received in an order of an arrangement of pixels in a row, into plural display data sets each composed of N display data, rearranges the plural display data sets such that one of the plural display data sets assigned to one of the plural display driving circuits is followed by one of the plural display data sets assigned to another of the plural display driving circuits succeeding the one of the plural display driving circuits, and outputs the rearranged display data sets to the plural display driving circuits.
    Type: Application
    Filed: May 14, 2004
    Publication date: December 30, 2004
    Inventors: Yoshihisa Ooishi, Hiroyuki Nitta, Junichi Maruyama, Naoki Takada, Kenichi Ono
  • Patent number: 6801178
    Abstract: A liquid crystal driving device for controlling a liquid crystal panel and a liquid crystal display apparatus. Reference voltages are generated in a data driver from input reference voltages, and reference voltages are selected in accordance with the settings of gray scale control registers thereby to control the gray scale voltages.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: October 5, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Nitta, Tsutomu Furuhashi, Makoto Kimura, Hirobumi Koshi, Takeshi Maeda
  • Publication number: 20040183792
    Abstract: A scan driver selects first four rows of pixels at a time and then sequentially selects second four rows of pixels for each row in double gate driving. A data driver supplies a tone voltage corresponding to black data to the first four row of pixels at a time and then sequentially supplies a tone voltage corresponding to display data to the second four rows of pixels.
    Type: Application
    Filed: February 24, 2004
    Publication date: September 23, 2004
    Inventors: Naoki Takada, Hiroyuki Nitta, Nobuyuki Koganezawa, Kikuo Ono, Takashi Shoji
  • Publication number: 20040164976
    Abstract: A display device of the present invention prevents the display flow of brightness lines on a screen. Lines of image data are inputted to a data driver circuit one after another for every horizontal scanning period of the image data. The data driver circuit alternately repeats (i) a first step for generating a display signal corresponding to each one of the lines of the image data one after another for a fixed period and outputting the display signal to a pixel array N-times (N being a natural number equal to or greater than 2) and (ii) a second step for generating a display signal which makes the luminance of the pixels lower than the luminance of the pixel in the first step for the fixed period and outputting the display signal to the pixel array M-times (M being a natural number smaller than N).
    Type: Application
    Filed: January 21, 2004
    Publication date: August 26, 2004
    Inventors: Masashi Nakamura, Hiroyuki Nitta, Nobuhiro Takeda, Masahiro Tanaka
  • Publication number: 20040080522
    Abstract: A fast-write, high picture-quality LCD (Liquid Crystal Display) compatible with a high-resolution, large-sized liquid crystal panel. An output amplifier circuit of a liquid crystal driver circuit includes an amplifier configuration, which functions as an amplifier that amplifies the predetermined gray-scale voltage for output and as an amplifier that buffers the predetermined gray-scale voltage and outputs with no amplification, and a circuit for switching the above two types of amplifiers. In each horizontal period, a liquid crystal panel is driven by the amplified output for a predetermined period and by the buffered output for the rest of the period. A pre-charge control circuit is provided to check whether the gray-scale voltage is to be amplified depending upon display data.
    Type: Application
    Filed: October 20, 2003
    Publication date: April 29, 2004
    Inventors: Hiroyuki Nitta, Kazuyoshi Kawabe, Satoru Tsunekawa, Hirobumi Koshi
  • Publication number: 20040027323
    Abstract: In a display device having a pixel array in which a plurality of pixels are arranged two-dimensionally along a first direction and a second direction, each of the pixels includes a pair of electrodes applying a voltage to liquid crystals, respective groups of the pixels arranged along the first direction form a plurality of pixel-rows juxtaposed along the second direction, and respective groups of the pixels arranged along the second direction form a plurality of pixel-columns juxtaposed along the first direction, the present invention repeats a first step for selecting every Y rows of the pixel-rows sequentially along the second direction N-times and applying an image signal to one of the pair of electrodes provided for each one of the pixels belonging to the each Y rows of the pixel-rows as selected, and a second step for selecting every Z rows of the pixel-rows sequentially along the second direction M-times and applying a blanking signal to the one of the pair of electrodes provided for each one of the pi
    Type: Application
    Filed: June 26, 2003
    Publication date: February 12, 2004
    Inventors: Masahiro Tanaka, Hiroyuki Nitta, Nobuhiro Takeda, Masashi Nakamura
  • Publication number: 20040001054
    Abstract: A hold-type display device for eliminating blurring without damaging the display brightness of moving images. The display device includes a pixel array including a plurality of pixels, a plurality of first signal lines, a plurality of second signal lines, a first driving circuit outputting scanning signals to the plurality of first signal lines, and a second driving circuit outputting display signals to the plurality of second signal lines. The first driving circuit repeats a step for sequentially selecting the first signal lines every Y lines for every N times and a step for selecting the first signal lines every Z lines for every M times which follows the N times. The second driving circuit repeats outputting N times the display signals and outputting M times a blanking signal which masks an image displayed on corresponding pixels.
    Type: Application
    Filed: March 20, 2003
    Publication date: January 1, 2004
    Inventors: Hiroyuki Nitta, Nobuyuki Koganezawa, Nobuhiro Takeda, Tsutomu Furuhashi, Masashi Nakamura
  • Patent number: 6661402
    Abstract: A fast-write, high picture-quality LCD (Liquid Crystal Display) compatible with a high-resolution, large-sized liquid crystal panel. An output amplifier circuit of a liquid crystal driver circuit includes an amplifier configuration, which functions as an amplifier that amplifies the predetermined gray-scale voltage for output and as an amplifier that buffers the predetermined gray-scale voltage and outputs with no amplification, and a circuit for switching the above two types of amplifiers. In each horizontal period, a liquid crystal panel is driven by the amplified output for a predetermined period and by the buffered output for the rest of the period. A pre-charge control circuit is provided to check whether the gray-scale voltage is to be amplified depending upon display data.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Nitta, Kazuyoshi Kawabe, Satoru Tsunekawa, Hirobumi Koshi