Abstract: An evaporation unit includes a first and second pipe conduits. The first and second pipe conduits each include a near-end part, a long circumference part, a junction part, a short circumference part, and a far-end part. Around a storage chamber, the first long circumference part extends in a first direction, the first junction part turns, and the first short circumference part extends in the first or second direction. The second short circumference part extends in the first direction, the second junction part turns, and the second long circumference part extends in the first or second direction. The first and second turning part located at the same position counted from the respective near-end part sides are disposed respectively on wall surfaces facing each other.

Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

Abstract: A microorganism having at least one SPX gene encoding SPX protein responsive to phosphorus deficiency, and characterized in that a function of the SPX protein is decreased or lost by introducing gene mutation into the SPX gene.

Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

Abstract: A thin film transistor 101 includes: a gate electrode 2, a semiconductor layer 4 disposed on the gate electrode via a gate insulating layer 3, a source electrode 8s disposed on a portion of the semiconductor layer 4 via a first contact layer Cs, and a drain electrode 8d disposed on another portion via a second contact layer Cd. The first and second contact layers have a multilayer structure including N (where N is an integer equal to or greater than 1) two-layer structures S(n) (where n is an integer not smaller than 1 and not greater than N), each two-layer structure S(n) including a first amorphous silicon layer 71 that is directly in contact with the source or drain electrode, a second amorphous silicon layer 72(n), and a third amorphous silicon layer 73(n) that is directly in contact with an upper face thereof.

Abstract: A thin film transistor 101 includes: an active layer 7 that is supported on a substrate 1 and includes a first region 7S, a second region 7D and a channel region 7C located between the first region and the second region; a gate electrode 11 that is arranged so as to overlap with at least the channel region of the active layer 7 with a gate insulating layer 9 therebetween; a source electrode 15s electrically connected to the first region 7S; and a drain electrode 15d electrically connected to the second region 7D, at least the channel region 7C of the active layer 7 having a layered structure that includes a first metal layer m1 arranged on a lower oxide semiconductor layer 71 and containing substantially no oxygen, and an upper oxide semiconductor layer 72 arranged on the first metal layer m1, wherein a thickness of the first metal layer m1 is smaller than a thickness of the lower oxide semiconductor layer 71 or the upper oxide semiconductor 72.

Abstract: An aspect of the present invention provides an internal and the like. The internal is easily handled and is capable of yielding a satisfactory defoaming effect. An internal (50) is used in a fluidized bed reaction device (1), in which a first material and a second material are brought into contact with each other and reacted with each other. The internal (50) is attached to a ceiling part of the fluidized bed reaction device (1), and includes a plurality of chains (21).

Abstract: A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region.

Abstract: A thin film transistor 101 includes: a gate electrode 2; a gate insulating layer 3; a semiconductor layer 4 including an amorphous semiconductor layer 4a and a crystalline semiconductor layer 4c that is disposed on a portion of the amorphous semiconductor layer 4a, the semiconductor layer 4 including an active region Rc that includes the crystalline semiconductor layer 4c and a portion of the amorphous semiconductor layer 4a, and the semiconductor layer 4 including first and second semiconductor regions Rs and Rd which respectively include first and second amorphous portions A1 and A2 that are located on opposite sides of the active region Rc; a protective insulating layer 5; first and second contact layers Cs and Cd disposed on the semiconductor layer 4 and the protective insulating layer 5; a source electrode 8s; and a drain electrode 8d.

Abstract: A microorganism having at least one SPX gene encoding SPX protein responsive to phosphorus deficiency, and characterized in that a function of the SPX protein is decreased or lost by introducing gene mutation into the SPX gene.

Abstract: A thin film transistor 101 includes: a gate electrode 2, a semiconductor layer 4 disposed on the gate electrode via a gate insulating layer 3, a source electrode 8s disposed on a portion of the semiconductor layer 4 via a first contact layer Cs, and a drain electrode 8d disposed on another portion via a second contact layer Cd. The first and second contact layers have a multilayer structure including N (where N is an integer equal to or greater than 1) two-layer structures S(n) (where n is an integer not smaller than 1 and not greater than N), each two-layer structure S(n) including a first amorphous silicon layer 71 that is directly in contact with the source or drain electrode, a second amorphous silicon layer 72(n), and a third amorphous silicon layer 73(n) that is directly in contact with an upper face thereof.

Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

Abstract: A thin film transistor (101) includes: a gate electrode (2) supported by a substrate (1); a gate insulating layer (3) covering the gate electrode; a semiconductor layer (4) being disposed on the gate insulating layer and including a polysilicon region (4p), the polysilicon region (4p) including a first region (Rs), a second region (Rd), and a channel region (Rc) that is located between the first region and the second region; a source electrode (8s) electrically connected to the first region; a drain electrode (8d) electrically connected to the second region; a protective insulating layer (5) disposed between the semiconductor layer and the source electrode and drain electrode; an i type semiconductor layer composed of an intrinsic semiconductor, the i type semiconductor layer being disposed between the protective insulating layer and the channel region so as to be directly in contact with a portion of the channel region; and a sidewall disposed on a side surface of the protective insulating layer.

Abstract: A thin film transistor (101) includes: a gate electrode (2) supported by a substrate (1); a gate insulating layer (3) covering the gate electrode; a semiconductor layer (4) being disposed on the gate insulating layer and including a polysilicon region (4p), the polysilicon region (4p) including a first region (Rs), a second region (Rd), and a channel region (Rc) that is located between the first region and the second region; a source electrode (8s) electrically connected to the first region; and a drain electrode (8d) electrically connected to the second region. Above a portion of the channel region, at least one protecting section (20) that is spaced apart from at least one of the first region and the second region is further included.

Abstract: A thin film transistor (101) includes: a gate electrode (2) supported by a substrate (1); a gate insulating layer (3) covering the gate electrode; a semiconductor layer (4) being disposed on the gate insulating layer and including a polysilicon region (4p), the polysilicon region (4p) including a first region (Rs) , a second region (Rd) , and a channel region (Rc) that is located between the first region and the second region; a source electrode (8s) electrically connected to the first region; and a drain electrode (8d) electrically connected to the second region. At least one i type semiconductor islet (10) composed of an intrinsic semiconductor is further included, the i type semiconductor islet being disposed above the channel region so as to be directly in contact with the channel region and having a band gap larger than that of the polysilicon region.

Abstract: A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region.

Abstract: An aspect of the present invention provides an internal and the like. The internal is easily handled and is capable of yielding a satisfactory defoaming effect. An internal (50) is used in a fluidized bed reaction device (1), in which a first material and a second material are brought into contact with each other and reacted with each other. The internal (50) is attached to a ceiling part of the fluidized bed reaction device (1), and includes a plurality of chains (21).

Abstract: A thin film transistor (101) includes: a gate electrode (2) supported on a substrate (1); a semiconductor layer (4) including a crystalline silicon region (4c), wherein the crystalline silicon region (4c) includes a channel region (Rc); a gate insulating layer (3); a source electrode (8s); and a drain electrode (8d), wherein the channel region (Rc) includes a plurality of first crystalline regions (C1) and at least one second crystalline region (C2), wherein the first crystalline regions (C1) are separated from each other by the second crystalline region (C2); each first crystalline region (C1) includes an n-type impurity at a higher concentration than the second crystalline region (C2); and an average grain diameter of silicon crystal grains in each first crystalline region (C1) is larger than an average grain diameter of silicon crystal grains in the second crystalline region (C2).

Abstract: A thin film transistor includes: an oxide semiconductor layer including a first region, a second region, and a channel region located between the first region and the second region; a gate electrode provided on the channel region with a gate insulating layer interposed therebetween; a source electrode electrically coupled with the first region; a drain electrode electrically coupled with the second region; and an upper insulating layer covering the oxide semiconductor layer and the gate electrode, wherein when viewed in a normal direction of the substrate, the gate electrode overlaps the channel region of the oxide semiconductor layer but overlaps none of the first region and the second region, a lateral surface of the gate electrode includes a first lateral surface portion located on the first region side and overlapping the oxide semiconductor layer and a second lateral surface portion located on the second region side and overlapping the oxide semiconductor layer, the upper insulating layer includes a firs

Abstract: A thin film transistor includes: an oxide semiconductor layer including a first region, a second region, and a channel region; a gate electrode provided on the channel region so as to overlap the channel region with a gate insulating layer interposed therebetween, the gate electrode overlapping the channel region but overlapping none of the first region and the second region; a source electrode electrically coupled with the first region; and a drain electrode electrically coupled with the second region. The channel region of the oxide semiconductor layer has a greater thickness than the first region and the second region, and the oxide semiconductor layer includes a lower layer and an upper layer provided on part of the lower layer. The channel region includes the upper layer and the lower layer, and each of the first region and the second region includes the lower layer but does not include the upper layer.