Patents by Inventor Hiroyuki Sugaya

Hiroyuki Sugaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6258686
    Abstract: A manufacturing method of a bipolar transistor that can reduce, without increasing capacitance between base-collector, withstand voltage deterioration and leakage between emitter-base is provided. On an upper surface of an active area of a semiconductor substrate on which an isolation structure is formed by a first insulating film, a first epitaxial growth layer is formed. Then, on an upper surface of a first epitaxial growth layer a third insulating layer is formed in an area larger than that of the first epitaxial growth layer. Thereafter, from a side surface of a first epitaxial growth layer, a second epitaxial growth layer is formed in an area larger than that of a third insulating layer. Thereafter, all over the surface of the semiconductor substrate a first poly-silicon layer, a fourth and fifth insulating layers are formed, an opening is opened with an area approximately equal with that of an active area, and inside the opening a second poly-silicon layer and emitter layer are formed.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Sugaya
  • Patent number: 5963822
    Abstract: According to a method of fabricating a selective epitaxial film, a thin insulating film serving as a mask is formed on the entire surface of a semiconductor substrate having a (100) plane. An opening portion reaching the semiconductor substrate is formed in a desired region of the thin insulating film. An epitaxial film is selectively grown in the opening portion. The semiconductor substrate having the selective epitaxial film formed thereon is annealed at at least a pressure of 1,000 Pa and at least a temperature of 800.degree. C. to fill a gap on the contact surface between the thin insulating film and the selective epitaxial film.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya
  • Patent number: 5926725
    Abstract: In a method of manufacturing a semiconductor device, to form an opening in an insulation film such as a silicon oxide on a semiconductor substrate in a reverse tapered sectional configuration such that no gap is formed between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film, the insulation film having the opening is subjected to a thermal process in an atmosphere of non-oxidizing gas including hydrogen elements such as hydrogen, silane or disilane gas. An opening is formed in the insulation film on the semiconductor substrate using isotropic etching. As a result of the above-described thermal process, decomposition of a silicon oxide proceeds from the interface between the insulation film and the semiconductor substrate at a side-wall of the opening to eventually form the opening in a reverse tapered sectional configuration at least in an edge portion thereof.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: July 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya, Shizue Hori
  • Patent number: 5877540
    Abstract: A semiconductor device. A semiconductor substrate has a first conductivity. A first insulating layer is on the semiconductor substrate and has an opening so that a portion of the semiconductor substrate is exposed. A semiconductor layer has a second conductivity on the portion. A region in said semiconductor layer prevents a leakage current caused by a minute defect and faceting.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Naruse, Hiroyuki Sugaya, Hidenori Saihara, Yoshiro Baba
  • Patent number: 5864180
    Abstract: A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shizue Hori, Yoshiro Baba, Hiroyuki Sugaya, Hiroshi Naruse
  • Patent number: 5480953
    Abstract: Disclosed is a hydrophilic material characterized in that the material comprises a copolymer composed of a monomer (A) having a polyalkylene oxide unit and a polymerizable carbon-carbon double bond in its molecule, a methacrylic ester monomer or an acrylic ester monomer (B) and a monomer (C) having a polymerizable carbon-carbon double bond other than the monomers (A) and (B), and the content of the monomer (C) is not less than 5% by weight and not more than 90% by weight, and a semipermeable membrane made therefrom. The present invention provides a hydrophilic material which can be dissolved in a solvent, can be easily formed and is excellent in antithrombotic and antifouling properties, and further provides an antithrombotic material and a semipermeable membrane. These materials can be appropriately used in the medical field and as water-absorbent and antifouling materials.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: January 2, 1996
    Assignee: Toray Industries, Inc.
    Inventors: Hiroyuki Sugaya, Masahiro Minaga, Ryozo Terada, Toshikazu Tayama, Kazumi Tanaka, Fumiaki Fukui
  • Patent number: 4655327
    Abstract: A descent slowing device is disclosed that includes a housing having an input driving shaft and a driving pulley fitted thereon and accommodating therein a gear train and an impeller adapted to be driven through the gear train by a driving pulley about which is trained a rope or line. When one end of the line descends owing to a load acting thereon to rotatively drive the driving pulley and hence the impeller, the rotation of the impeller is restrained by rotation control oil or similar viscous fluid in which the impeller is immersed, thereby controlling the descent of the load at a constant slow speed. According to the invention, the impeller comprises four blades, the rotating speed ratio of the impeller to the input driving shaft being more than 40:1. Moreover, the driving pulley is formed with a rope receiving groove comprising line abutting projections and non-contact recesses alternately arranged.
    Type: Grant
    Filed: October 31, 1984
    Date of Patent: April 7, 1987
    Assignee: Lonseal Corporation
    Inventors: Hisatsugu Tomioka, Tazuo Waki, Hiroyuki Sugaya