Patents by Inventor Hiroyuki Tenmei
Hiroyuki Tenmei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160148865Abstract: The present invention aims to provide an electronic circuit board with insulation reliability improved by increasing volume resistivity of a ceramics substrate fabricated by an aerosol deposition method, a semiconductor device using it and a manufacturing method therefor. The present invention provides the electronic circuit board which includes a metal material, and an insulating film formed on a front surface of the metal material and including an inorganic material containing a crystal of a grain diameter of 10 to 20 nm and in which the insulating layer is less than 0.08 g/cm3 in amount of moisture which it contains. In addition, the present invention provides the manufacturing method for the electronic circuit board in which aerosol which contains particles configuring the insulating layer is injected to the metal material to form the insulating layer on the metal material and either the metal material front surface or the insulating layer front surface is heated.Type: ApplicationFiled: August 19, 2013Publication date: May 26, 2016Inventors: Kazuaki NAOE, Hiroyuki TENMEI, Masashi NISHIKI
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Patent number: 8937390Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: March 6, 2014Date of Patent: January 20, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Publication number: 20140183730Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 8704352Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: January 6, 2010Date of Patent: April 22, 2014Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Patent number: 8334465Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: GrantFiled: September 30, 2008Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Patent number: 7754581Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.Type: GrantFiled: December 14, 2007Date of Patent: July 13, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
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Publication number: 20100171213Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: January 6, 2010Publication date: July 8, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 7618847Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: GrantFiled: August 7, 2008Date of Patent: November 17, 2009Assignees: Elpida Memory, Inc., Hitachi, Ltd.Inventors: Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano, Hiroaki Ikeda, Masakazu Ishino
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Publication number: 20090134498Abstract: The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki IKEDA, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama, Yasuhiro Naka, Nae Hisano, Hisashi Tanie, Kunihiko Nishi, Hiroyuki Tenmei
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Publication number: 20090109641Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: ApplicationFiled: September 30, 2008Publication date: April 30, 2009Applicant: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Publication number: 20090072414Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: ApplicationFiled: August 7, 2008Publication date: March 19, 2009Inventors: Hiroyuki TENMEI, Kunihiko NISHI, Yasuhiro NAKA, Nae HISANO, Hiroaki IKEDA, Masakazu ISHINO
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Publication number: 20080164575Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.Type: ApplicationFiled: December 14, 2007Publication date: July 10, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
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Publication number: 20080136024Abstract: In a semiconductor device provided by preventing connection failure caused by misalignment of a semiconductor element having fine and narrow-pitched bumps, a guide for preventing the misalignment is formed by an insulating resin layer around a connection electrode. The insulating resin layer has a thickness defined in relation to an angle ? formed by a side wall of the opening and alignment accuracy ? for the bump. Specifically, the thickness of the insulating resin layer may be ? tan ? or more.Type: ApplicationFiled: November 29, 2007Publication date: June 12, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yasuhiro NAKA, Hiroyuki Tenmei, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO
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Patent number: 7378333Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.Type: GrantFiled: June 29, 2005Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Patent number: 7084498Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.Type: GrantFiled: October 17, 2002Date of Patent: August 1, 2006Assignee: Renesas Technology Corp.Inventors: Yoshihide Yamaguchi, Shigeharu Tsunoda, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
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Patent number: 7057283Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide ?-ray shielding of the semiconductor device.Type: GrantFiled: April 16, 2004Date of Patent: June 6, 2006Assignee: Hitachi, Ltd.Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Publication number: 20060091553Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.Type: ApplicationFiled: December 13, 2005Publication date: May 4, 2006Applicant: Hitachi, Ltd.Inventors: Yasunori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
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Patent number: 7002250Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.Type: GrantFiled: August 16, 2001Date of Patent: February 21, 2006Assignee: Renesas Technology Corp.Inventors: Hiroshi Hozoji, Yoshihide Yamaguchi, Naoya Kanda, Shigeharu Tunoda, Hiroyuki Tenmei
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Patent number: 6998713Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.Type: GrantFiled: April 27, 2004Date of Patent: February 14, 2006Assignee: Hitachi, Ltd.Inventors: Yasumori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
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Publication number: 20050245061Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.Type: ApplicationFiled: June 29, 2005Publication date: November 3, 2005Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura