Abstract: According to embodiments, in a case that a source voltage is lowered and a potential difference between the source voltage and a ripple terminal voltage is below a constant potential difference, the ripple terminal voltage is lowered until the ripple terminal voltage reaches a first threshold value when a lowered value of the source voltage is equal to or larger than a predetermined voltage that exceeds the first threshold value by the constant potential difference, and the ripple terminal voltage is lowered until the ripple terminal voltage reaches a second threshold value smaller than the first threshold value when the lowered value of the source voltage is below the predetermined voltage.

Abstract: According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.

Abstract: An n-channel integrated circuit device (n is an integer of 1 or greater) for muting an audio signal includes a control circuit configured to generate a control signal and a delayed control signal, a charging and discharging circuit configured to charge and discharge a time constant control terminal according to the control signal and the delayed control signal, an N-th voltage-to-current converting circuit (N is an integer from 1 to n) configured to generate a (2N?1)-th current corresponding to a voltage on the time constant control terminal and a (2N)-th current corresponding to an intermediate voltage, a (2N?1)-th mirror circuit configured to copy the (2N?1)-th current to generate (4N?3)-th and (4N?2)-th intermediate currents, a (2N)-th mirror circuit configured to copy the (2N)-th current to generate (4N?1)-th and (4N)-th intermediate currents, a (2N?1)-th selecting and combining circuit configured to combine a (2N?1)-th mute control current using the (4N?3)-th intermediate current and the (4N?1)-th interm

Abstract: According to embodiments, in a case that a source voltage is lowered and a potential difference between the source voltage and a ripple terminal voltage is below a constant potential difference, the ripple terminal voltage is lowered until the ripple terminal voltage reaches a first threshold value when a lowered value of the source voltage is equal to or larger than a predetermined voltage that exceeds the first threshold value by the constant potential difference, and the ripple terminal voltage is lowered until the ripple terminal voltage reaches a second threshold value smaller than the first threshold value when the lowered value of the source voltage is below the predetermined voltage.

Abstract: According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.

Abstract: A power amplifier system including a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal to which a control signal is supplied from outside, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, and a bias circuit which supplies a bias voltage to the power amplifier circuit, and a bias start-up circuit controlling the startup operation of the bias circuit.

Abstract: A power amplification device includes a BTL amplification circuit including a first amplification circuit and a second amplification circuit, the first amplification circuit including a first output transistor, a first power detection circuit, a second output transistor, and a second power detection circuit, the second amplification circuit including a third output transistor, a third power detection circuit, a fourth output transistor, and a fourth power detection circuit, a first comparator which compares output values of the first and fourth power detection circuits, and a second comparator which compares output values of the second and third power detection circuits.

Abstract: An n-channel integrated circuit device (n is an integer of 1 or greater) for muting an audio signal includes a control circuit configured to generate a control signal and a delayed control signal, a charging and discharging circuit configured to charge and discharge a time constant control terminal according to the control signal and the delayed control signal, an N-th voltage-to-current converting circuit (N is an integer from 1 to n) configured to generate a (2N?1)-th current corresponding to a voltage on the time constant control terminal and a (2N)-th current corresponding to an intermediate voltage, a (2N?1)-th mirror circuit configured to copy the (2N?1)-th current to generate (4N?3)-th and (4N?2)-th intermediate currents, a (2N)-th mirror circuit configured to copy the (2N)-th current to generate (4N?1)-th and (4N)-th intermediate currents, a (2N?1)-th selecting and combining circuit configured to combine a (2N?1)-th mute control current using the (4N?3)-th intermediate current and the (4N?1)-th interm

Abstract: A power amplification device includes a BTL amplification circuit including a first amplification circuit and a second amplification circuit, the first amplification circuit including a first output transistor, a first power detection circuit, a second output transistor, and a second power detection circuit, the second amplification circuit including a third output transistor, a third power detection circuit, a fourth output transistor, and a fourth power detection circuit, a first comparator which compares output values of the first and fourth power detection circuits, and a second comparator which compares output values of the second and third power detection circuits.

Abstract: A power amplifier system including a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal to which a control signal is supplied from outside, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, and a bias circuit which supplies a bias voltage to the power amplifier circuit, and a bias start-up circuit controlling the startup operation of the bias circuit.

Abstract: An amplifier circuit of a BTL system is disclosed, which comprises a first operational amplifier which outputs an output signal having a same phase as an input signal input to a signal input terminal, a second operational amplifier which outputs an output signal having an opposite phase to the input signal, a voltage divider which generates a midpoint voltage of the input signal, a first resistor connected between an output terminal and a negative phase input terminal of the first operational amplifier, second and third resistors connected in series between the negative phase input terminals of the first and second operational amplifiers, a fourth resistor connected between an output terminal and the negative phase input terminal of the second operational amplifier, and an impedance converter connected between a midpoint voltage node of the voltage divider and a series-connection node of the second and third resistors.

Abstract: The present invention provides a power amplifier system that includes a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, a bias start-up circuit that is controlled by an input of the control terminal, an output of the negative potential detection circuit, and the potential of the ripple terminal, and controls a bias start-up signal, a power amplifier IC that has a bias circuit which is controlled to be started up by the bias start-up signal, and has its output node for outputting a power amplifier bias voltage connected to the ripple terminal, and a ripple filter capacitor externally connected to the ripple terminal of the power amplifier IC.

Abstract: An amplifier circuit of a BTL system is disclosed, which comprises a first operational amplifier which outputs an output signal having a same phase as an input signal input to a signal input terminal, a second operational amplifier which outputs an output signal having an opposite phase to the input signal, a voltage divider which generates a midpoint voltage of the input signal, a first resistor connected between an output terminal and a negative phase input terminal of the first operational amplifier, second and third resistors connected in series between the negative phase input terminals of the first and second operational amplifiers, a fourth resistor connected between an output terminal and the negative phase input terminal of the second operational amplifier, and an impedance converter connected between a midpoint voltage node of the voltage divider and a series-connection node of the second and third resistors.

Abstract: A power amplifier includes an input circuit, three power supply lines with voltages successively decreasing in an order of first, second and third power supply lines, a push-side driving circuit and a pull-side driving circuit which receive control signals from the input circuit, three driving signal lines which are led out of the driving circuits, three output transistors which have current paths connected at one ends to the first, second and third power supply lines, and have gates connected to the three driving signal lines, respectively, an output terminal which is commonly connected to the other ends of the current paths of the output transistors, an impedance circuit which adjusts a gate impedance of the output transistor connected to the third power supply line, and a feedback circuit connected between the output terminal and the input circuit.

Abstract: The present invention provides a power amplifier system that includes a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, a bias start-up circuit that is controlled by an input of the control terminal, an output of the negative potential detection circuit, and the potential of the ripple terminal, and controls a bias start-up signal, a power amplifier IC that has a bias circuit which is controlled to be started up by the bias start-up signal, and has its output node for outputting a power amplifier bias voltage connected to the ripple terminal, and a ripple filter capacitor externally connected to the ripple terminal of the power amplifier IC.

Abstract: A power amplifier includes an input circuit, three power supply lines with voltages successively decreasing in an order of first, second and third power supply lines, a push-side driving circuit and a pull-side driving circuit which receive control signals from the input circuit, three driving signal lines which are led out of the driving circuits, three output transistors which have current paths connected at one ends to the first, second and third power supply lines, and have gates connected to the three driving signal lines, respectively, an output terminal which is commonly connected to the other ends of the current paths of the output transistors, an impedance circuit which adjusts a gate impedance of the output transistor connected to the third power supply line, and a feedback circuit connected between the output terminal and the input circuit.

Abstract: The present invention relates to a semiconductor output circuit that protects a circuit including such a reverse operation as reverses the potentials of a collector and an emitter of a bipolar transistor. A cathode of a protective diode is connected to a P type side of a base-emitter PN junction of a bipolar transistor constituting a semiconductor output circuit, while an anode of the protective diode is connected to an N type side of the base-emitter PN junction. By positively operating the bipolar transistor in a reverse direction with a reverse current gain &bgr;R>1, a reverse voltage between a collector and an emitter of the bipolar transistor is precluded from exceeding Veco to prevent the transistor from being broken down due to its reverse operation.

Abstract: A power amplifier comprises a pair of power-supply rails, a power-supply voltage divider, an intermediate power-supply line, a first and second BTL amplifiers, and a first to fourth switching circuits. The power-supply rails are composed of a first power-supply line to which a power-supply potential is applied and a second power-supply line to which the ground potential is applied. The power-supply divider produces an intermediate potential by dividing the voltage between the power-supply rails in two and supplies it to the intermediate power-supply line. The first BTL amplifier is provided between the second power-supply line and the intermediate power-supply line. The second BTL amplifier is provided between the first power-supply line and the intermediate power-supply line. The first and second BTL amplifiers each include an output bridge circuit.