Patents by Inventor Hiroyuki Uchida

Hiroyuki Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8693239
    Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein the memory layer has a lamination structure of a Co—Fe—B layer and an element belonging to any one of 1A group, 2A group, 3A group, 5A group, or 6A group, an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventors: Masanori Hosomi, Kazuhiro Bessho, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20140042573
    Abstract: There is disclosed a memory element including a layered structure including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer; and an insulating layer provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of a layered structure, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, in regard to the insulating layer that comes into contact with the memory layer, and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film, and the memory layer includes at least one of non-magnetic metal and oxide in addition to a Co—Fe—B magnetic layer.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 13, 2014
    Applicant: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida
  • Patent number: 8637947
    Abstract: A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: January 28, 2014
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Hiroyuki Uchida
  • Publication number: 20140013021
    Abstract: In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.
    Type: Application
    Filed: December 18, 2012
    Publication date: January 9, 2014
    Applicant: TOPS SYSTEMS CORPORATION
    Inventors: Yukoh Matsumoto, Hiroyuki Uchida
  • Patent number: 8625342
    Abstract: A storage element includes: a storage layer which retains information by a magnetization state of a magnetic substance; a magnetization pinned layer having magnetization which is used as the basis of the information stored in the storage layer; and an interlayer of a non-magnetic substance provided between the storage layer and the magnetization pinned layer. The storage element is configured to store information by reversing magnetization of the storage layer using spin torque magnetization reversal generated by a current passing in a laminate direction of a layer structure including the storage layer, the interlayer, and the magnetization pinned layer, and when the saturation magnetization of the storage layer and the thickness thereof are represented by Ms (emu/cc) and t (nm), respectively, (1489/Ms)?0.593<t<(6820/Ms)?1.55 holds.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: January 7, 2014
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20130338814
    Abstract: A numerical controller has a work supporting control part that supports a work in manufacture or maintenance of a machine tool to be controlled. The work supporting control part has a motor drive command storage part that stores motor drive commands associated with work items. When a work item is selected on a screen, a guidance that describes the content of the work item and a setting item or check item associated with the work item are displayed on the screen. Then, in response to an operation signal output from an operation part, a motor drive command associated with the selected work item is read from the motor drive command storage part and output to a driving control part.
    Type: Application
    Filed: March 13, 2013
    Publication date: December 19, 2013
    Applicant: FANUC CORPORATION
    Inventors: Hiroyuki UCHIDA, Susumu MAEKAWA
  • Patent number: 8611139
    Abstract: There is disclosed a memory element including a layered structure including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer; and an insulating layer provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of a layered structure, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, in regard to the insulating layer that comes into contact with the memory layer, and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film, and the memory layer includes at least one of non-magnetic metal and oxide in addition to a Co—Fe—B magnetic layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida
  • Patent number: 8598671
    Abstract: Disclosed herein is a storage element, including: a storage layer configured to retain information based on a magnetization state of a magnetic material; and a magnetization pinned layer configured to be provided for the storage layer with intermediary of a tunnel barrier layer, wherein the tunnel barrier layer has a thickness not less than or equal to 0.1 nm to not more than or equal to 0.6 nm and interface roughness less than 0.5 nm, and information is stored in the storage layer through change in direction of magnetization of the storage layer by applying a current in a stacking direction and injecting a spin-polarized electron.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
  • Publication number: 20130307100
    Abstract: A magnetic memory device including a memory layer having a vertical magnetization on the layer surface, of which the direction of magnetization is changed according to information; and a reference layer provided against the memory layer, and being a basis of information while having a vertical magnetization on the layer surface, wherein the memory device memorizes the information by reversing the magnetization of the memory layer by a spin torque generated when a current flows between layers made from the memory layer, the nonmagnetization layer and the reference layer, and a coercive force of the memory layer at a memorization temperature is 0.7 times or less than a coercive force at room temperature, and a heat conductivity of a center portion of an electrode formed on one side of the memory layer in the direction of the layer surface is lower than a heat conductivity of surroundings thereof.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20130302913
    Abstract: A method of manufacturing a storage element by forming a magnetic layer; and forming a tunnel barrier layer on the magnetic layer, wherein, n the forming a tunnel barrier layer, the tunnel barrier layer is formed to a predetermined thickness in at least two steps in a divided manner.
    Type: Application
    Filed: June 20, 2013
    Publication date: November 14, 2013
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
  • Patent number: 8573081
    Abstract: A shaft part is formed with a rolling groove (5) on which rolling elements (4) roll. At least the rolling groove (5) is induction hardened with no generation of black colored oxidized scale after the induction hardening. A surface of the induction hardened rolling groove (5) is used “as is” as a rolling surface. The surface roughness Ra of the induction hardened surface “as is” of the rolling groove (5) is less than 1.0. The ratio of effective hardened depth of a hardened layer is between 0.15 and 0.45.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: November 5, 2013
    Assignee: NTN Corporation
    Inventors: Hiroyuki Uchida, Kenji Ouwa, Kazuho Mimura, Kazuhiko Yoshida
  • Patent number: 8565013
    Abstract: A storage element includes a storage layer that stores information on the basis of a magnetization state of a magnetic material; a fixed magnetization layer that has a magnetization serving as a reference of the information stored in the storage layer; an interlayer that is formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a cap layer that is provided to be adjacent to the storage layer and opposite to the interlayer; and a metal cap layer that is provided to be adjacent to the cap layer and opposite to the storage layer.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 22, 2013
    Assignee: Sony Corporation
    Inventors: Kazuhiro Bessho, Masanori Hosomi, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Tetsuya Asayama, Hiroyuki Uchida
  • Patent number: 8559219
    Abstract: A storage element includes a storage layer which has magnetization vertical to the film surface and of which the direction of magnetization changes, a magnetization fixed layer which has magnetization vertical to the film surface serving as a reference of information, and an insulating layer, and the direction of magnetization of the storage layer changes by injecting spin-polarized electrons in the laminated direction of the layer structure so as to perform information recording, the size of an effective demagnetizing field that the storage layer receives is configured to be smaller than a saturated magnetization amount of the storage layer, and a ferromagnetic layer material constituting the storage layer has CoFeB as the base material and an anti-corrosive element is added to the base material.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Kazuhiro Bessho, Hiroyuki Ohmori, Yutaka Higo, Tetsuya Asayama, Kazutaka Yamane
  • Patent number: 8547731
    Abstract: Disclosed herein is a memory device, including: a memory element including a memory layer for holding therein information in accordance with a magnetization state of a magnetic material, a fixed magnetization layer which is provided on the memory layer through a non-magnetic layer and whose direction of a magnetization is fixed to a direction parallel with a film surface, and a magnetic layer which is provided on a side opposite to the fixed magnetization layer relative to the memory layer through a non-magnetic layer and whose direction of a magnetization is a direction vertical to the film surface; and a wiring through which a current is caused to flow through the memory element in a direction of lamination of the layers of the memory element.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: October 1, 2013
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8546897
    Abstract: A magnetic memory element includes a memory layer, a reference layer, and a spin-injection layer provided between the memory layer and the reference layer. The reference layer has a structure in which at least two CoPt layers containing 20 atomic % or more and 50 atomic % or less of Pt and having a thickness of 1 nm or more and 5 nm or less are stacked with a Ru layer provided therebetween. The thickness of the Ru layer is 0.45±0.05 nm or 0.9±0.1 nm. In addition, the axis of 3-fold crystal symmetry of the CoPt layers is oriented perpendicularly to the film surface. The reference layer includes a high spin polarization layer of 1.5 nm or less containing Co or Fe as a main component at an interface with the spin-injection layer.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: October 1, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20130235872
    Abstract: A router, includes: a routing table memory unit configured to store a routing table and be capable of reading and writing the routing table at any time, the routing table being destination information of a packet; a search engine unit which has a transfer information base memory unit and which is configured to search for a destination of the packet based on a transfer information base; a power supply unit configured to supply power to the routing table memory unit and the transfer information base memory unit; and a control unit configured to control the power supply unit such that the power is supplied to the non-volatile memory when the non-volatile memory is operated, and the power supply is interrupted when the non-volatile memory is not operated.
    Type: Application
    Filed: February 27, 2013
    Publication date: September 12, 2013
    Applicant: SONY CORPORATION
    Inventors: Kazuhiro Bessho, Masanori Hosomi, Hiroyuki Ohmori, Yutaka Higo, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8514600
    Abstract: A power conversion apparatus includes a current sensor that detects a phase current flowing through a phase current line, a first phase-voltage detection unit that detects a first phase voltage in the phase current line with a potential in a P line as a reference, a second phase-voltage detection unit that detects a second phase voltage in the phase current line with a potential in an N line as a reference, an estimation unit that estimates a zero-cross point timing of the phase current based on magnitude and symbol of the first and second phase voltage, a calculation unit that obtains a correction value with respect to a detection value of the current sensor according to the detection value of the current sensor at the estimated zero-cross point timing, and a correction unit that corrects a detection value of the current sensor by using the obtained correction value.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: August 20, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masafumi Ichihara, Hiroyuki Uchida
  • Patent number: 8497139
    Abstract: A magnetic memory device including a memory layer having a vertical magnetization on the layer surface, of which the direction of magnetization is changed according to information; and a reference layer provided against the memory layer, and being a basis of information while having a vertical magnetization on the layer surface, wherein the memory device memorizes the information by reversing the magnetization of the memory layer by a spin torque generated when a current flows between layers made from the memory layer, the nonmagnetization layer and the reference layer, and a coercive force of the memory layer at a memorization temperature is 0.7 times or less than a coercive force at room temperature, and a heat conductivity of a center portion of an electrode formed on one side of the memory layer in the direction of the layer surface is lower than a heat conductivity of surroundings thereof.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8491697
    Abstract: [Problem]To provide a method for producing an electrocatalyst having no compositional scatter, wherein nano-level alloy catalyst molecules with an ordered particle size are supported in a highly dispersed state. [Means of Solution] The method includes the steps of preparing a reverse micelle solution by mixing two or more catalyst precursors selected from among metal salts and/or metal complexes, a solvent having hydrophilic groups and a non-aqueous solvent, forming alloy particles in the reverse micelle by adding a non-aqueous solution having a reducing action to the reverse micelle and heating, and supporting the alloy particles on a carrier.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: July 23, 2013
    Assignee: Yamanashi University
    Inventors: Masahiro Watanabe, Hiroyuki Uchida
  • Patent number: 8472243
    Abstract: Disclosed herein is a storage apparatus including a cell array configured to include storage devices arranged to form an array. Each of the storage device has: a storage layer for storing information as the state of magnetization of a magnetic substance; a fixed-magnetization layer having a fixed magnetization direction; and a tunnel insulation layer sandwiched between the storage layer and the fixed-magnetization layer. In an operation to write information on the storage layer, a write current is generated to flow in the layer-stacking direction of the storage layer and the fixed-magnetization layer in order to change the direction of the magnetization of the storage layer. The cell array is divided into a plurality of cell blocks. The thermal stability of the storage layer of any particular one of the storage devices has a value peculiar to the cell block including the particular storage device.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: June 25, 2013
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Hiroyuki Uchida, Hiroyuki Ohmori, Kazuhiro Bessho, Masanori Hosomi, Kazutaka Yamane