Patents by Inventor Hiroyuki Yaegashi

Hiroyuki Yaegashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050269572
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Application
    Filed: July 18, 2005
    Publication date: December 8, 2005
    Applicant: Sharp Corporation
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Publication number: 20050255621
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Application
    Filed: July 18, 2005
    Publication date: November 17, 2005
    Applicant: Sharp Corporation
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Publication number: 20050250264
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Application
    Filed: July 18, 2005
    Publication date: November 10, 2005
    Applicant: Sharp Corporation
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Patent number: 6939750
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: September 6, 2005
    Assignee: Fujitsu Display Technologies Corporation
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Publication number: 20050162080
    Abstract: An organic EL display apparatus is disclosed that includes a substrate, a thin film transistor formed on the substrate, an insulation film formed on the substrate in a manner covering the thin film transistor, and an organic EL element formed on the insulation film. The insulation film is formed with a recess portion. The organic EL element is formed in a manner contacting the thin film transistor via the recess portion formed in the insulation film.
    Type: Application
    Filed: March 22, 2005
    Publication date: July 28, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki Yaegashi
  • Publication number: 20040232424
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Application
    Filed: May 5, 2004
    Publication date: November 25, 2004
    Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Publication number: 20030153110
    Abstract: A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an interlayer insulating film which is a film stack with mutually different dielectric constants and which covers the gate electrode, a source region contact hole and a drain region contact hole which are formed on the interlayer insulating film, a pixel electrode connected to the source region through the source region contact hole, a first conductive film connected to the drain region through the drain region contact hole and formed of the same film as that of the pixel electrode, and a second conductive film connected to the drain region through the first conductive film.
    Type: Application
    Filed: December 9, 2002
    Publication date: August 14, 2003
    Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATION.
    Inventors: Kazushige Hotta, Yoshio Kurosawa, Seii Sato, Takuya Watanabe, Hiroyuki Yaegashi
  • Publication number: 20030151049
    Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.
    Type: Application
    Filed: December 19, 2002
    Publication date: August 14, 2003
    Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
    Inventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
  • Patent number: 6376861
    Abstract: A thin film transistor comprises a gate electrode 18 formed on a substrate 10, a gate insulation film 20, a semiconductor layer 22, a source electrode 36a and a drain electrode 36b. The gate electrode, the source electrode or the drain electrode include a first conductor film 12, a second conductor film 14 and a third conductor film 16. The first conductor film is formed of a metal selected out of Al, Cu and Ag, or an alloy of a metal, as a main component, selected out of Al, Cu and Ag, and has the side surfaces sloped. The second conductor film is formed of a film of Mo containing nitrogen, or an alloy of Mo, as a main component, containing nitrogen, and has the side surfaces sloped. The third conductor film is formed of Mo or an alloy of Mo as a main component.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: April 23, 2002
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Yaegashi, Takuya Watanabe, Tetsuya Kida, Akira Komorita
  • Patent number: 6255706
    Abstract: A thin film transistor wherein at least one of (1) a gate electrode and/or a scanning line therefor and (2) source/drain electrode and/or signal lines therefor comprises a laminated wiring structure in which a main wiring layer formed of a metal selected from Al and Cu or an alloy based on the metal is sandwiched between an underlying wiring layer and an overlaying wiring layer, the underlying and overlaying wiring layers being formed of a material based on a metal or alloy of metals and containing nitrogen, the metal being selected from Ti, Mo, W, Cr, Al and Cu, and the materials used in the underlying and overlaying wiring layers being different from each other. Alternatively, the underlying and overlaying wiring layers are formed of a material based on the same metal or alloy of metals and containing nitrogen, the metal being selected from Ti, Mo, W, Cr, Al and Cu, and contents of nitrogen in the underlying and overlaying wiring layers being different from each other.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: July 3, 2001
    Assignee: Fujitsu Limited
    Inventors: Takuya Watanabe, Hiroyuki Yaegashi, Hideki Noto, Tetsuya Kida