Patents by Inventor Hiroyuki Yoshimoto

Hiroyuki Yoshimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8643117
    Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: February 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
  • Publication number: 20130341729
    Abstract: Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 26, 2013
    Inventors: Digh Hisamoto, Shinichi Saito, Akio Shima, Hiroyuki Yoshimoto
  • Publication number: 20130213696
    Abstract: A metal-clad laminate, including metal foil, and a first resin layer arranged on the metal foil, the first resin layer including an epoxy resin and a fluoropolymer with a curable functional group. Also disclosed is a method of producing the metal-clad laminate.
    Type: Application
    Filed: October 25, 2011
    Publication date: August 22, 2013
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Yoshihisa Yamamoto, Hiroyuki Yoshimoto, Hideto Nakagawa
  • Patent number: 8466236
    Abstract: The invention provides a fluororesin composition capable of providing a molded article having low relative dielectric constant, excellent in a temperature stability and causing only small transmission losses. The invention is a fluororesin composition wherein a rate of change in relative dielectric constant between 25° C. and 80° C. of a molded article produced therefrom under a standard condition is not greater than 0.2%.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: June 18, 2013
    Assignee: Daikin Industries, Ltd.
    Inventors: Hiroyuki Yoshimoto, Hirokazu Yukawa, Yasuhiko Sawada, Taku Yamanaka, Masamichi Sukegawa
  • Publication number: 20120227999
    Abstract: The present invention provides an electric wire having excellent weather resistance and durability. The present invention relates to: an electric wire, comprising: a conductor; an insulating layer formed around the periphery of the conductor; and an outer layer formed around the periphery of the insulating layer, wherein the outer layer is formed by application of a weatherproof coating material; and a production method thereof.
    Type: Application
    Filed: November 9, 2010
    Publication date: September 13, 2012
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Masamichi Sukegawa, Hiroyuki Yoshimoto
  • Patent number: 8183635
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Sugii, Ryuta Tsuchiya, Shinichiro Kimura, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto
  • Publication number: 20120018807
    Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
    Type: Application
    Filed: January 18, 2010
    Publication date: January 26, 2012
    Applicant: HITACHI, LTD.
    Inventors: Ryuta Tsuchiya, Nobuyuki Sugii, Yusuke Morita, Hiroyuki Yoshimoto, Takashi Ishigaki, Shinichiro Kimura
  • Publication number: 20110097984
    Abstract: A variable duct apparatus that controls outside air flowing in to a radiator includes a variable louver that is provided so as to extend in the vehicle width direction between a grille opening and a radiator of a vehicle, and regulates the amount of outside air admitted to the radiator, a lower louver that is provided so as to extend in the vehicle width direction between an air inlet and the radiator, and regulates the amount of outside air admitted to the radiator, and a link mechanism that coordinates and synchronizes the variable louver and the lower louver with each other, and interrupts the coordination between the variable louver and the lower louver upon application of an external force to the lower louver to thereby permit swinging of the lower louver.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 28, 2011
    Applicant: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Masami Hasegawa, Hiroyuki Yoshimoto
  • Patent number: 7890898
    Abstract: Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: February 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichi Saito, Digh Hisamoto
  • Publication number: 20100258869
    Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Inventors: Yusuke MORITA, Ryuta Tsuchiya, Takashi Ishigaki, Hiroyuki Yoshimoto, Nobuyuki Sugii, Shinichiro Kimura
  • Publication number: 20100258872
    Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Inventors: Nobuyuki SUGII, Ryuta TSUCHIYA, Shinichiro KIMURA, Takashi ISHIGAKI, Yusuke MORITA, Hiroyuki YOSHIMOTO
  • Patent number: 7732531
    Abstract: The present invention provides a molded article comprising a polytetrafluoroethylene resin (A) and a thermoplastic resin (B) having a melting point of not lower than 100° C. but lower than 322° C., wherein the maximum peak temperature of the endothermic curve appearing on the crystal melting curve of the above polytetrafluoroethylene resin (A) as measured by a differential scanning calorimeter is higher by at least 3° C. than the maximum peak temperature of the endothermic curve appearing on the crystal melting curve of the above polytetrafluoroethylene resin (A) after heating to a temperature of not lower than 340° C. as measured by the differential scanning calorimeter.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: June 8, 2010
    Assignee: Daikin Industries, Ltd.
    Inventors: Hiroyuki Yoshimoto, Yasuhiko Sawada, Shunji Kasai, Shuji Tagashira
  • Publication number: 20100087599
    Abstract: The invention provides a fluororesin composition capable of providing a molded article having low relative dielectric constant, excellent in a temperature stability and causing only small transmission losses. The invention is a fluororesin composition wherein a rate of change in relative dielectric constant between 25° C. and 80° C. of a molded article produced therefrom under a standard condition is not greater than 0.2%.
    Type: Application
    Filed: February 18, 2008
    Publication date: April 8, 2010
    Applicant: DAIKIN INDUSTRIES , LTD.
    Inventors: Hiroyuki Yoshimoto, Hirokazu Yukawa, Yasuhiko Sawada, Taku Yamanaka, Masamichi Sukegawa
  • Publication number: 20090132974
    Abstract: Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.
    Type: Application
    Filed: January 31, 2008
    Publication date: May 21, 2009
    Inventors: Hiroyuki YOSHIMOTO, Nobuyuki Sugii, Shinichi Saito, Digh Hisamoto
  • Publication number: 20080281067
    Abstract: The present invention provides a polytetrafluoroethylene powder having moldability/processability as well as electrical characteristics in microwave bands. The present invention is a modified polytetrafluoroethylene powder which has (1) a dielectric loss tangent at 12 GHz of not higher than 2.0×10?4 and (2) a cylinder extrusion pressure of not higher than 45 MPa at a reduction ratio of 1600.
    Type: Application
    Filed: April 4, 2005
    Publication date: November 13, 2008
    Inventors: Yoshinori Nanba, Yasuhiko Sawada, Shunji Kasai, Shuji Tagashira, Makoto Ono, Takahiro Taira, Hiroyuki Yoshimoto
  • Patent number: 7435466
    Abstract: It is an object of the present invention to provide a polytetrafluoroethylene-based-resin tube high in longitudinal tensile strength and a method of producing the same. The present invention provides a polytetrafluoroethylene-based-resin tube characterized in that the tensile strength thereof in the longitudinal direction is not lower than 60 MPa.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: October 14, 2008
    Assignee: Daikin Industries, Ltd.
    Inventors: Hiroyuki Yoshimoto, Yasuhiko Sawada, Shunji Kasai, Shuji Tagashira
  • Publication number: 20080227880
    Abstract: The present invention provides a molded porous body with very small air bubbles distributed therein as well as a filter using the porous body. The present invention is related to a porous body comprising a polytetrafluoroethylene-based resin and a thermoplastic resin other than the polytetrafluoroethylene-based resin, and having a specific gravity exceeding 1.80 but less than 2.18 and a percent conversion to crystals of not higher than 50%.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Hiroyuki YOSHIMOTO, Hirokazu Yukawa, Yasuhiko Sawada, Taku Yamanaka, Masamichi Sukegawa
  • Patent number: 7387834
    Abstract: The present invention provides a polytetrafluoroethylene molded article, particularly a PTFE molded article for high-frequency insulation, which is excellent in various electric properties and mechanical properties in a high frequency range of 3 to 30 GHz. The present invention also provides PTFE fine powder, which is excellent in extrusion moldability and capable of providing the molded article, and a process for preparing the same. More specifically, the present invention relates to a polytetrafluoroethylene fine powder having a standard specific gravity of 2.180 to 2.225, which is obtained by contacting polytetrafluoroethylene fine powder having a standard specific gravity of 2.180 to 2.225 with a fluorine radical source, wherein tan? at 12 GHz of a film comprising the powder, which is obtained by cooling at 5 to 50° C./second after baking, is at most 2.0×10?4.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: June 17, 2008
    Assignee: Daikin Industries, Ltd.
    Inventors: Tetsuo Shimizu, Michio Asano, Makoto Ono, Yoshinori Nanba, Shunji Kasai, Shinichi Yano, Hiroyuki Yoshimoto
  • Publication number: 20080020159
    Abstract: The present invention provides a modified polytetrafluoroethylene fine powder which can be processed into molded articles high in thermal stability, chemical resistance and transparency and for which the extrusion pressure can be lowered. The present invention is a modified polytetrafluoroethylene fine powder, wherein the cylinder extrusion pressure at a reduction ratio of 1600 is not higher than 50 MPa and the haze value of molded article a for measurement formed therefrom is not higher than 60.
    Type: Application
    Filed: November 16, 2005
    Publication date: January 24, 2008
    Applicant: Daikin Industries, LTD.
    Inventors: Takahiro Taira, Hiroyuki Yoshimoto, Taketo Kato, Yasuhiko Sawada
  • Publication number: 20070009727
    Abstract: The present invention provides a porous polytetrafluoroethylene molded article, wherein the specific gravity of the above porous polytetrafluoroethylene molded article is 0.9 to 2.0 and the aspect ratio of a void formed within the above molded article is not lower than 1 but not higher than 3.
    Type: Application
    Filed: August 25, 2004
    Publication date: January 11, 2007
    Inventors: Yasuhiko Sawada, Hiroyuki Yoshimoto, Shunji Kasai, Shuji Tagashira