Patents by Inventor Hisao Asakura
Hisao Asakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6895346Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: GrantFiled: October 10, 2002Date of Patent: May 17, 2005Assignee: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
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Publication number: 20050035428Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: ApplicationFiled: September 22, 2004Publication date: February 17, 2005Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada
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Patent number: 6841405Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: GrantFiled: October 10, 2002Date of Patent: January 11, 2005Assignee: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Patent number: 6812540Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: GrantFiled: November 19, 2002Date of Patent: November 2, 2004Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada
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Patent number: 6780660Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: GrantFiled: October 10, 2002Date of Patent: August 24, 2004Assignee: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Patent number: 6771077Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: GrantFiled: April 19, 2002Date of Patent: August 3, 2004Assignee: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Patent number: 6770496Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: GrantFiled: October 10, 2002Date of Patent: August 3, 2004Assignee: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Publication number: 20030199111Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: ApplicationFiled: October 10, 2002Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Publication number: 20030199107Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: ApplicationFiled: April 19, 2002Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
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Publication number: 20030197522Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: ApplicationFiled: October 10, 2002Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Publication number: 20030199110Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: ApplicationFiled: October 10, 2002Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
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Publication number: 20030197523Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.Type: ApplicationFiled: October 10, 2002Publication date: October 23, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
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Publication number: 20030111707Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: ApplicationFiled: November 19, 2002Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada
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Patent number: 6566719Abstract: The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.Type: GrantFiled: December 21, 1999Date of Patent: May 20, 2003Assignee: Hitachi, Ltd.Inventor: Hisao Asakura
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Patent number: 6399453Abstract: Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.Type: GrantFiled: June 27, 2001Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Ryo Nagai, Norikatsu Takaura, Hisao Asakura
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Publication number: 20010054725Abstract: This invention obtains desired operating characteristics from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.Type: ApplicationFiled: June 27, 2001Publication date: December 27, 2001Inventors: Ryo Nagai, Norikatsu Takaura, Hisao Asakura
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Patent number: 6287912Abstract: A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.Type: GrantFiled: September 3, 1999Date of Patent: September 11, 2001Assignee: Hitachi, Ltd.Inventors: Hisao Asakura, Yoshitaka Tadaki, Toshihiro Sekiguchi, Ryo Nagai, Masafumi Miyamoto, Masayuki Nakamura
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Patent number: 6265254Abstract: The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.Type: GrantFiled: December 30, 1999Date of Patent: July 24, 2001Assignee: Hitachi, Ltd.Inventor: Hisao Asakura
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Patent number: 6198128Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.Type: GrantFiled: September 7, 1999Date of Patent: March 6, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hisao Asakura, Yoshitaka Tadaki, Toshihiro Sekiguchi, Ryo Nagai, Masafumi Miyamoto, Masayuki Nakamura, Shinichi Miyatake, Tsuyuki Suzuki, Masahiro Hyoma
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Patent number: 6077735Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.Type: GrantFiled: August 28, 1996Date of Patent: June 20, 2000Assignee: Texas Instruments IncorporatedInventors: Yuji Ezaki, Shinya Nishio, Fumiaki Saitoh, Hideo Nagasawa, Toshiyuki Kaeriyama, Songsu Cho, Hisao Asakura, Jun Murata, Yoshitaka Tadaki, Toshihiro Sekiguchi, Keizo Kawakita