Abstract: The present disclosure provides systems and methods for sequencing nucleic acid molecules using tunneling labels. A sequence of a nucleic acid molecule may be identified with high accuracy using a chip comprising sensors, wherein each individual sensor may comprise at least two electrodes separated by a gap. The electrodes may be configured to generate at least one electrical signal upon binding of a tunneling label associated with a nucleotide. Epigenetic information can also be determined at the same time as a nucleic acid sequence.

Abstract: A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.

Abstract: A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.

Abstract: A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.

Abstract: A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes.

Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.

Abstract: A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.

Abstract: Disclosed are: a semiconductor light-emitting element which fulfills all of high migration preventing properties, high permeability and low film production cost; a protective film for a semiconductor light-emitting element; and a process for producing the protective film. In a semiconductor light-emitting element comprising multiple semiconductor layers (12-14) formed on a substrate (11) and electrode portions (15, 16) and electrode portions (17, 18) which act as electrodes for the multiple semiconductor layers (12-14), an SiN film (31) having a thickness of 35 nm or more and comprising silicon nitride covers the surrounds of the multiple semiconductor layers (12-14), the electrode portions (15, 16) and the electrode portions (17, 18) and an SiO film (32) having a higher thickness than that of the SiN film (31) and comprising silicon oxide covers the surround of the SiN film (31), as protective films for the semiconductor light-emitting element.

Abstract: Disclosed are: a semiconductor light-emitting element that fulfills all of having high migration prevention, high transmittance, and low film-production cost; the protective film of the semiconductor light-emitting element; and a method for fabricating same. To this end, in the semiconductor light-emitting element-which has: a plurality of semiconductor layers (12-14) formed on a substrate (11); and electrode sections (15, 16) and other electrode sections (17, 18) that are the electrodes of the plurality of semiconductor layers (12-14)—as the protective film thereof, the surroundings of the plurality of semiconductor layers (12-14), the electrode sections (15, 16), and the other electrode sections (17, 18) are covered by a SiN film (21) comprising silicon nitride of which the quantity of Si—H bonds in the film is less than 1.0×1021 bonds/cm3.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intr

Abstract: There is provided a semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; a first insulation film formed between the source electrode and the drain electrode and having a band-like opening parallel to the drain electrode and the source electrode; a gate electrode formed at the opening in the first insulation film; a second insulation film formed on the first insulation film in such a manner as to cover a surface of the gate electrode; and a source field plate electrode which is formed on the second insulation film and the source electrode and an end portion of which on the drain electrode side is spaced from the second insulation film, thereby suppressing degradation in device performance.

Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

Abstract: A semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; an insulation film formed between the source electrode and the drain electrode and having a band-like opening in parallel to the source electrode and the drain electrode; a gate electrode formed at the opening in the insulation film; and a drain-side field plate electrode formed integrally with the gate electrode on the drain electrode side of the gate electrode and having a drain electrode side end portion spaced from the insulation film, thus restraining degradation in performance.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.