Abstract: Semiconductor devices having improved electromigration resistance in their connections through dielectric layers are described. Where a conductive metal line overlies a dielectric layer and makes contact to a lower conductive structure through the dielectric layer by virtue of a conductive member, such as a tungsten plug or metal contact, the conductive metal line is provided with an end portion not otherwise connected to a conductive structure. The end portion serves as a reservoir of extra conductive material supplying the conductive metal line as the line is depleted through stress migration and/or electromigration.

Abstract: An electrically programmable read-only memory cell includes a single crystal silicon pillar having the active region of the memory cell. A memory array of the cells may be configured to act as an EPROM array, an EEPROM array, or a flash EEPROM array. A silicon spacer lies adjacent to each of the silicon pillars and acts as a floating gate for its particular memory cell. A memory cell may have a cell area that is less than one square micron. In an EPROM or a flash EEPROM array, no field isolation is required between the memory cells within the array. Processes for forming the memory cells and the memory array are disclosed.

Abstract: A conformal titanium nitride film having a preferred <111> crystal orientation is formed by chemically vapor depositing the film in two separate steps. In the first deposition step a titanium nitride layer (22) having poor step coverage and a preferred <111> crystal orientation is formed. In the second deposition step a second conformal layer of titanium nitride (24) is insitu deposited onto the first titanium nitride layer (22), wherein during the deposition the first titanium nitride layer (22) acts as a crystallographic seed layer for the second titanium nitride layer (24). As a result, a titanium nitride layer exhibiting a preferred <111> crystal orientation and good step coverage is achieved.

Abstract: An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.

Abstract: An electrically programmable read-only memory cell includes a single crystal silicon pillar having the active region of the memory cell. A memory array of the cells may be configured to act as an EPROM array, an EEPROM array, or a flash EEPROM array. A silicon spacer lies adjacent to each of the silicon pillars and acts as a floating gate for its particular memory cell. A memory cell may have a cell area that is less than one square micron. In an EPROM or a flash EEPROM array, no field isolation is required between the memory cells within the array. Processes for forming the memory cells and the memory array are disclosed.

Abstract: The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.

Abstract: A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.

Abstract: The surface area of a polysilicon electrode is increased by sputtering non-coalescing islands (20) of aluminum onto a silicon dioxide layer (18), which is overlying the polysilicon electrode. The sputtering process allows uniform island formation to be achieved independent of the deposition surface. The non-coalescing islands are then used as a mask, and a portion of the buffer layer (22) and a portion of the polysilicon electrode (26) are etched to form pillar-like regions (30) within the polysilicon electrode.

Abstract: A local interconnect structure is formed in a semiconductor device. In one form, the semiconductor device has two conductive features (one of 54) and (56) which are to be electrically connected. A layer of metal (62), for instance titanium, is deposited on the device. The layer of metal is patterned to form a strap (64) which connects the two conductive features. After patterning the layer of metal to form the strap, the strap is thermally nitrided to form a conductive metal nitride local interconnect (66).