Patents by Inventor Hisashi Shichijo
Hisashi Shichijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8134204Abstract: A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without adding any process steps. Both n-channel and p-channel versions may be fabricated in CMOS ICs with an n-type buried layer. Furthermore, the inventive transistor may be fabricated in an IC built in an SOI wafer. The width of the compensation region may be varied across multiple instances of the inventive DEMOS transistor to provide a capability for handling multiple signals with different voltage levels in the same IC without adding fabrication steps. The compensation region may be biased by a control voltage to modulate the depletion of the drain extension and provide a capability for handling multiple signal voltage levels in a single transistor.Type: GrantFiled: August 6, 2009Date of Patent: March 13, 2012Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Hisashi Shichijo
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Patent number: 7915905Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.Type: GrantFiled: April 16, 2010Date of Patent: March 29, 2011Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Publication number: 20100197053Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.Type: ApplicationFiled: April 16, 2010Publication date: August 5, 2010Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Patent number: 7719299Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.Type: GrantFiled: April 2, 2008Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Patent number: 7692217Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.Type: GrantFiled: November 30, 2007Date of Patent: April 6, 2010Assignee: Texas Instruments IncorporatedInventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
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Publication number: 20100032755Abstract: A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without adding any process steps. Both n-channel and p-channel versions may be fabricated in CMOS ICs with an n-type buried layer. Furthermore, the inventive transistor may be fabricated in an IC built in an SOI wafer. The width of the compensation region may be varied across multiple instances of the inventive DEMOS transistor to provide a capability for handling multiple signals with different voltage levels in the same IC without adding fabrication steps. The compensation region may be biased by a control voltage to modulate the depletion of the drain extension and provide a capability for handling multiple signal voltage levels in a single transistor.Type: ApplicationFiled: August 6, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel BENAISSA, Hisashi SHICHIJO
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Publication number: 20090251164Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Baher S. Haroun, Gaurav Chandra, Vijaya Bhaskar Rentala, Venkatesh Srinivasan, Hisashi Shichijo, Krishnaswamy Nagaraj
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Publication number: 20090140346Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
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Patent number: 7250334Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.Type: GrantFiled: July 31, 2004Date of Patent: July 31, 2007Assignee: Texas Instruments IncorporatedInventors: Darius L. Crenshaw, Byron L. Williams, Alwin Tsao, Hisashi Shichijo, Satyavolu S. Papa Rao, Kenneth D. Brennan, Steven A. Lytle
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Publication number: 20060024899Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.Type: ApplicationFiled: July 31, 2004Publication date: February 2, 2006Inventors: Darius Crenshaw, Byron Williams, Alwin Tsao, Hisashi Shichijo, Satyavolu Papa Rao, Kenneth Brennan, Steven Lytle
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Patent number: 6764892Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.Type: GrantFiled: May 27, 2003Date of Patent: July 20, 2004Assignee: Texas Instruments IncorporatedInventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
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Patent number: 6753202Abstract: A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.Type: GrantFiled: May 28, 2003Date of Patent: June 22, 2004Assignee: Texas Instruments IncorporatedInventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Publication number: 20030230704Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprisingType: ApplicationFiled: May 28, 2003Publication date: December 18, 2003Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Publication number: 20030222273Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.Type: ApplicationFiled: May 27, 2003Publication date: December 4, 2003Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
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Patent number: 6621064Abstract: A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.Type: GrantFiled: May 3, 2001Date of Patent: September 16, 2003Assignee: Texas Instruments IncorporatedInventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Patent number: 6576959Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.Type: GrantFiled: September 5, 2001Date of Patent: June 10, 2003Assignee: Texas Instruments IncorporatedInventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
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Patent number: 6512280Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.Type: GrantFiled: May 16, 2001Date of Patent: January 28, 2003Assignee: Texas Instruments IncorporatedInventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Publication number: 20020171097Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.Type: ApplicationFiled: May 16, 2001Publication date: November 21, 2002Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Publication number: 20020162945Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprisingType: ApplicationFiled: May 3, 2001Publication date: November 7, 2002Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
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Publication number: 20020145164Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.Type: ApplicationFiled: September 5, 2001Publication date: October 10, 2002Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo